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library ieee;
use ieee.std_logic_1164.all;
entity asgn02 is
port (s0 : std_logic;
r : out std_logic_vector (2 downto 0));
end asgn02;
architecture behav of asgn02 is
begin
process (s0) is
begin
r <= "000";
if s0 = '1' then
r (1) <= '1';
end if;
end process;
end behav;
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