blob: 4d20a2730ba54e42f0baf24849a08ab258552285 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
|
library ieee;
use ieee.std_logic_1164.all;
entity aggr03 is
port (a : std_logic_vector (7 downto 0);
b : out std_logic_vector (7 downto 0));
end aggr03;
architecture rtl of aggr03 is
signal r : std_logic_vector (7 downto 0);
begin
b <= r or a;
r <= (7 downto 2 => '0', others => '1');
end rtl;
|
