blob: d65c812eac91a7c5460645a241b963eb1716f0a4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
|
library ieee;
use ieee.std_logic_1164.all;
entity acomp is
port (x: in std_ulogic; y: out std_ulogic);
end entity;
architecture aarch of acomp is
begin
y <= x;
end architecture;
|