testsuite/gna/issue679/repro.vhdl


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entity repro is
end repro;

architecture behav of repro is
   signal clk : bit;
   signal cyc: bit;
   signal wen : bit;
   signal lw : bit;
begin
   -- psl default clock is clk;

   -- psl c1: assert always lw -> cyc and (next not(wen))
   --  report "error";
end;