blob: 7807666b7a2065bc91e4b0663dbe6d425467a8d3 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
entity repro1b is
port (b : bit_vector);
end entity;
architecture a of repro1b is
signal c : b'subtype;
begin
c <= b;
assert c'left = 7;
assert c'right = 0;
end architecture;
entity repro1 is
end entity;
architecture tb of repro1 is
signal s : bit_vector(7 downto 0);
begin
DUT: entity work.repro1b
port map (b => s);
end architecture;
|
