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type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); -- WKT:3
type integer is range <>;
subtype natural is integer range 0 to 2147483647;
type std_ulogic_vector is array (natural range <>) of std_ulogic;
subtype std_logic_vector is std_ulogic_vector;
type t_wishbone_slave_in is record
dat: std_logic_vector;
end record;
design
package standard:
package textio:
package std_logic_1164:
package numeric_std:
package wishbone_pkg:
instance wb_demux_tb:
signal wbs_i: t_wishbone_slave_in(dat (31 downto 0)): #1-#32
process stimulus:
instance dut:
port-in wbs_i: t_wishbone_slave_in(dat (31 downto 0)): #1-#32
Time is 0 fs
#1: 'U' (0)
#2: 'U' (0)
#3: 'U' (0)
#4: 'U' (0)
#5: 'U' (0)
#6: 'U' (0)
#7: 'U' (0)
#8: 'U' (0)
#9: 'U' (0)
#10: 'U' (0)
#11: 'U' (0)
#12: 'U' (0)
#13: 'U' (0)
#14: 'U' (0)
#15: 'U' (0)
#16: 'U' (0)
#17: 'U' (0)
#18: 'U' (0)
#19: 'U' (0)
#20: 'U' (0)
#21: 'U' (0)
#22: 'U' (0)
#23: 'U' (0)
#24: 'U' (0)
#25: 'U' (0)
#26: 'U' (0)
#27: 'U' (0)
#28: 'U' (0)
#29: 'U' (0)
#30: 'U' (0)
#31: 'U' (0)
#32: 'U' (0)
Time is 0 fs
#1: '1' (3)
#2: '1' (3)
#3: '0' (2)
#4: '1' (3)
#5: '1' (3)
#6: '1' (3)
#7: '1' (3)
#8: '0' (2)
#9: '1' (3)
#10: '0' (2)
#11: '1' (3)
#12: '0' (2)
#13: '1' (3)
#14: '1' (3)
#15: '0' (2)
#16: '1' (3)
#17: '1' (3)
#18: '0' (2)
#19: '1' (3)
#20: '1' (3)
#21: '1' (3)
#22: '1' (3)
#23: '1' (3)
#24: '0' (2)
#25: '1' (3)
#26: '1' (3)
#27: '1' (3)
#28: '0' (2)
#29: '1' (3)
#30: '1' (3)
#31: '1' (3)
#32: '1' (3)
Time is 100000000 fs
#1: '1' (3)
#2: '1' (3)
#3: '0' (2)
#4: '1' (3)
#5: '1' (3)
#6: '1' (3)
#7: '1' (3)
#8: '0' (2)
#9: '1' (3)
#10: '0' (2)
#11: '1' (3)
#12: '0' (2)
#13: '1' (3)
#14: '1' (3)
#15: '0' (2)
#16: '1' (3)
#17: '1' (3)
#18: '0' (2)
#19: '1' (3)
#20: '1' (3)
#21: '1' (3)
#22: '1' (3)
#23: '1' (3)
#24: '0' (2)
#25: '1' (3)
#26: '1' (3)
#27: '1' (3)
#28: '0' (2)
#29: '1' (3)
#30: '1' (3)
#31: '1' (3)
#32: '1' (3)
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