1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AbstractMmPkg.all;
entity testbench is
end entity testbench;
architecture TB of testbench is
signal AWADDR : std_logic_vector(6 downto 0);
signal AWPROT : std_logic_vector(2 downto 0);
signal AWVALID : std_logic;
signal AWREADY : std_logic;
signal WDATA : std_logic_vector(31 downto 0);
signal WSTRB : std_logic_vector(3 downto 0);
signal WVALID : std_logic;
signal WREADY : std_logic;
signal BRESP : std_logic_vector(1 downto 0);
signal BVALID : std_logic;
signal BREADY : std_logic;
signal ARADDR : std_logic_vector(6 downto 0);
signal ARPROT : std_logic_vector(2 downto 0);
signal ARVALID : std_logic;
signal ARREADY : std_logic;
signal RDATA : std_logic_vector(31 downto 0);
signal RRESP : std_logic_vector(1 downto 0);
signal RVALID : std_logic;
signal RREADY : std_logic;
signal ACLK : std_logic;
signal ARESETn : std_logic;
signal rec : AbstractMmRecType(
writedata(31 downto 0),
readdata(31 downto 0),
address(4 downto 0),
byteen(3 downto 0)
);
begin
BFM: entity work.axi_master
generic map (
DATAWIDTH => 32,
ADDRWIDTH => AWADDR'length
) port map(
-- AXI interface,
AWADDR => AWADDR,
AWPROT => AWPROT,
AWVALID => AWVALID,
AWREADY => AWREADY,
WDATA => WDATA,
WSTRB => WSTRB,
WVALID => WVALID,
WREADY => WREADY,
BRESP => BRESP,
BVALID => BVALID,
BREADY => BREADY,
ARADDR => ARADDR,
ARPROT => ARPROT,
ARVALID => ARVALID,
ARREADY => ARREADY,
RDATA => RDATA,
RRESP => RRESP,
RVALID => RVALID,
RREADY => RREADY,
ACLK => ACLK,
ARESETn => ARESETn,
-- AMR interface
amr => rec
);
end architecture TB;
|
