testsuite/gna/issue326/foo.vhdl


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entity foo is
	port(a, b: out bit);
end entity foo;
architecture bug of foo is
begin
	a <= '0', '1' after 1 ns, '0' after 2 ns, '1' after 3 ns;
	process(a)
	begin
		b <= not a;
	end process;
end architecture bug;