blob: bf7b5351029faa20cbb52e3a64f224c61100cbcb (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
|
library ieee;
use ieee.std_logic_1164.all;
entity aggregate_bug is
end entity aggregate_bug;
architecture rtl of aggregate_bug is
signal vec : std_logic_vector(7 downto 0);
begin
vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice
process
begin
wait for 1 ns;
report to_string(vec);
wait for 1 ns;
std.env.finish;
end process;
end architecture rtl;
|
