blob: 6fe2faef9336c4114993d709047feab976b11947 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
library IEEE;
use IEEE.std_logic_1164.all;
entity clock is
port(
interval: in time;
EN : in std_logic;
CLK : out std_logic
);
end clock;
architecture behave of clock is
begin
clock : process
begin
loop
exit when EN = '0';
CLK <= not '1';
wait for interval;
CLK <= not '0';
wait for interval;
end loop;
CLK <= '0';
wait until EN = '1';
end process;
end architecture;
|
