blob: 4d6e9b7b1323eaaffa2789d0b32fbc3d95f8402b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_delayline is
generic (
delay : natural := 10
);
end entity;
architecture rtl of tb_delayline is
signal clk : std_logic := '0';
signal i, o : std_logic_vector(7 downto 0);
begin
-- 100 Mhz clock
process
procedure pulse is
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end pulse;
begin
for j in 1 to 9 loop
i <= std_logic_vector(to_unsigned (j + 16 * (15 - j), 8));
pulse;
end loop;
i <= x"f0";
pulse;
i <= x"1e";
for j in 1 to 9 loop
pulse;
assert o = std_logic_vector(to_unsigned (j + 16 * (15 - j), 8))
severity failure;
end loop;
pulse;
assert o = x"f0" severity failure;
report "Test is ok";
wait;
end process;
-- Device Under Test
c0: entity work.delayline(rtl)
generic map (
delay => delay
)
port map (
clk => clk,
i => i,
o => o
);
end architecture;
|
