blob: 1b7dd854b99e06a6fd997ace174c1f9412bf52ff (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
|
Library ieee;
use ieee.std_logic_1164.all;
entity ex1 is
end entity;
architecture tb of ex1 is
signal a,b : std_logic := '0';
signal clk_sys : std_logic;
default clock is rising_edge(clk_sys);
begin
gen_clock_proc : process
begin
clk_sys <= '1';
wait for 5 ns;
clk_sys <= '0';
wait for 5 ns;
end process;
test_proc : process
begin
a <= '1';
wait for 50 ns;
std.env.finish;
end process;
my_seq : assert never a[=3];
end architecture tb;
|
