testsuite/gna/issue1655/repro.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

entity repro_ch is
  generic (v : natural);
  port (i : bit);
end;

architecture behav of repro_ch is
begin
  assert v > 5;
end;

entity repro is
end;

architecture behav of repro is
  component comp is
    port (i : bit);
  end component;

  signal s : bit;

  for inst : comp use entity work.repro_ch(behav);
begin
  inst: comp port map (i => s);
end;