blob: 17e3b59073eb0fb1ff9b4a52f9f6ed697f7530e8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
entity ap_a_04 is
end entity ap_a_04;
library ieee; use ieee.std_logic_1164.all;
architecture test of ap_a_04 is
signal a, b, y : std_ulogic;
begin
-- code from book
y <= a or b;
-- end code from book
a <= '0', '1' after 10 ns;
b <= '0', '1' after 9223372036854775802 ns, '0' after 10 ns, '1' after 15 ns;
end architecture test;
|
