testsuite/gna/issue1469/ent1.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity ent1 is
end;

architecture arch of ent1 is

    procedure f(a : std_logic_vector(open)) is
    begin
      report "a(a'high)=" & std_logic'image(a(a'high));
    end procedure;

begin
  f ("0110");
end;