testsuite/gna/issue106/ent.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ent is
end entity ent;

architecture arch of ent is
  signal test: natural;
begin
  LL: if test=10 generate
  elsif test=5 generate
  end generate;
end architecture arch;