testsuite/gna/bug069/bug1.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

library IEEE;
use IEEE.std_logic_1164.all;

entity bug1 is
end entity bug1;

architecture behavioural of bug1 is

  signal outEn      : std_logic;

begin

  outEn <= 1;

end architecture behavioural;