blob: 7def1ed7adf9bbd0baab93086f06320b8620c9bd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
-- VHDL code formatter.
-- Copyright (C) 2019 Tristan Gingold
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <gnu.org/licenses>.
with Vhdl.Nodes; use Vhdl.Nodes;
with Vhdl.Prints;
package Vhdl.Formatters is
type Format_Level is
(
-- No re-formatting.
-- Trailing spaces are removed, keywords are converted to lower case.
Format_None,
-- Format_None + start of each line is adjusted
Format_Indent,
-- Format_Indent + spaces between tokens is adjusted
Format_Space
);
-- Format/pretty print the file F.
procedure Format (F : Iir_Design_File;
Level : Format_Level;
Flag_Realign : Boolean;
First_Line : Positive := 1;
Last_Line : Positive := Positive'Last);
-- Reindent all lines of F between [First_Line; Last_Line] to HANDLE.
procedure Indent_String (F : Iir_Design_File;
Handle : Vhdl.Prints.Vstring_Acc;
First_Line : Positive := 1;
Last_Line : Positive := Positive'Last);
end Vhdl.Formatters;
|
