blob: b1514766ef6ec132e55c576b94439fbcf19daacf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
|
-- Statements synthesis.
-- Copyright (C) 2017 Tristan Gingold
--
-- This file is part of GHDL.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-- MA 02110-1301, USA.
with Types; use Types;
with Vhdl.Nodes; use Vhdl.Nodes;
with Netlists; use Netlists;
with Synth.Values; use Synth.Values;
with Synth.Context; use Synth.Context;
with Synth.Environment; use Synth.Environment;
package Synth.Stmts is
procedure Synth_Subprogram_Association (Subprg_Inst : Synth_Instance_Acc;
Caller_Inst : Synth_Instance_Acc;
Inter_Chain : Node;
Assoc_Chain : Node);
procedure Synth_Assignment_Prefix (Syn_Inst : Synth_Instance_Acc;
Pfx : Node;
Dest_Valtyp : out Valtyp;
Dest_Off : out Uns32;
Dest_Voff : out Net;
Dest_Rdwd : out Width);
procedure Synth_Assignment (Syn_Inst : Synth_Instance_Acc;
Target : Node;
Val : Valtyp;
Loc : Node);
function Synth_Read_Memory (Syn_Inst : Synth_Instance_Acc;
Obj : Value_Acc;
Off : Uns32;
Voff : Net;
Typ : Type_Acc;
Loc : Node) return Valtyp;
function Synth_User_Function_Call
(Syn_Inst : Synth_Instance_Acc; Expr : Node) return Valtyp;
-- Operation implemented by a user function.
function Synth_User_Operator (Syn_Inst : Synth_Instance_Acc;
Left_Expr : Node;
Right_Expr : Node;
Expr : Node) return Valtyp;
-- Generate netlists for concurrent statements STMTS.
procedure Synth_Concurrent_Statements
(Syn_Inst : Synth_Instance_Acc; Stmts : Node);
procedure Synth_Verification_Unit
(Syn_Inst : Synth_Instance_Acc; Unit : Node);
-- For iterators.
function In_Range (Rng : Discrete_Range_Type; V : Int64) return Boolean;
procedure Update_Index (Rng : Discrete_Range_Type; Idx : in out Int64);
private
-- There are 2 execution mode:
-- * static: it is like simulation, all the inputs are known, neither
-- gates nor signals are generated. This mode is used during
-- elaboration and when all inputs of a subprogram are known.
-- * dynamic: inputs can be wires so gates are generated. But many types
-- (like file or access) cannot be handled.
type Mode_Type is (Mode_Static, Mode_Dynamic);
type Loop_Context (Mode : Mode_Type);
type Loop_Context_Acc is access all Loop_Context;
type Loop_Context (Mode : Mode_Type) is record
Prev_Loop : Loop_Context_Acc;
Loop_Stmt : Node;
case Mode is
when Mode_Dynamic =>
-- Set to true so that inner loops have to declare W_Quit.
Need_Quit : Boolean;
-- Value of W_En at the entry of the loop.
Saved_En : Net;
-- Set to 0 in case of exit for the loop.
-- Set to 0 in case of exit/next for outer loop.
-- Initialized to 1.
W_Exit : Wire_Id;
-- Set to 0 if this loop has to be quited because of an
-- exit/next for an outer loop. Initialized to 1.
W_Quit : Wire_Id;
-- Mark to release wires.
Wire_Mark : Wire_Id;
when Mode_Static =>
S_Exit : Boolean;
S_Quit : Boolean;
end case;
end record;
-- Context for sequential statements.
type Seq_Context (Mode : Mode_Type) is record
Inst : Synth_Instance_Acc;
Cur_Loop : Loop_Context_Acc;
Ret_Value : Valtyp;
Ret_Typ : Type_Acc;
Nbr_Ret : Int32;
case Mode is
when Mode_Dynamic =>
-- Enable execution.
W_En : Wire_Id;
W_Ret : Wire_Id;
-- Return value.
W_Val : Wire_Id;
Ret_Init : Net;
when Mode_Static =>
S_En : Boolean;
end case;
end record;
end Synth.Stmts;
|
