1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
|
-- Gates declaration
-- Copyright (C) 2017 Tristan Gingold
--
-- This file is part of GHDL.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-- MA 02110-1301, USA.
package Netlists.Gates is
-- Dyadic gates. Inputs and output have the same width.
Id_And : constant Module_Id := 3;
Id_Or : constant Module_Id := 4;
Id_Xor : constant Module_Id := 5;
Id_Nand : constant Module_Id := 6;
Id_Nor : constant Module_Id := 7;
Id_Xnor : constant Module_Id := 8;
Id_Add : constant Module_Id := 9;
Id_Sub : constant Module_Id := 10;
Id_Mul : constant Module_Id := 11;
subtype Dyadic_Module_Id is Module_Id range Id_And .. Id_Mul;
Id_Buf : constant Module_Id := 13;
Id_Not : constant Module_Id := 14;
Id_Neg : constant Module_Id := 15;
subtype Monadic_Module_Id is Module_Id range Id_Buf .. Id_Neg;
Id_Eq : constant Module_Id := 16;
Id_Ne : constant Module_Id := 17;
Id_Ule : constant Module_Id := 18;
Id_Sle : constant Module_Id := 19;
Id_Ult : constant Module_Id := 20;
Id_Slt : constant Module_Id := 21;
Id_Uge : constant Module_Id := 22;
Id_Sge : constant Module_Id := 23;
Id_Ugt : constant Module_Id := 24;
Id_Sgt : constant Module_Id := 25;
subtype Compare_Module_Id is Module_Id range Id_Eq .. Id_Sgt;
Id_Red_And : constant Module_Id := 26;
Id_Red_Or : constant Module_Id := 27;
subtype Reduce_Module_Id is Module_Id range Id_Red_And .. Id_Red_Or;
Id_Concat2 : constant Module_Id := 28;
Id_Concat3 : constant Module_Id := 29;
Id_Concat4 : constant Module_Id := 30;
subtype Concat_Module_Id is Module_Id range Id_Concat2 .. Id_Concat4;
Id_Split2 : constant Module_Id := 31;
Id_Split3 : constant Module_Id := 32;
-- Inputs: s, i0, i1
-- Output: o
Id_Mux2 : constant Module_Id := 33;
-- Inputs: s, i0, i1, s2, s3
-- Output: o
Id_Mux4 : constant Module_Id := 34;
-- Like a wire: the output is equal to the input, but could be elimited
-- at any time. Isignal has an initial value.
Id_Signal : constant Module_Id := 35;
Id_Isignal : constant Module_Id := 36;
Id_Output : constant Module_Id := 37;
Id_Port : constant Module_Id := 38;
-- Note: initial values must be constant nets.
--
-- A simple D flip-flop. The D input is stored on a rising edge of CLK.
-- Q is the output. For falling edge dff, use a NOT gate on the CLK
-- input.
-- Inputs: CLK, D
-- Output: Q
Id_Dff : constant Module_Id := 40;
-- A DFF with an asynchronous reset. Note that the asynchronous reset
-- has priority over the clock. When RST is asserted, the value is
-- set to RST_VAL.
-- Inputs: CLK, D, RST, RST_VAL
-- Output: Q
Id_Adff : constant Module_Id := 41;
-- A simple DFF with an initial value (must be constant). This is
-- for FPGAs.
Id_Idff : constant Module_Id := 42;
-- A DFF with an asynchronous reset and an initial value.
Id_Iadff : constant Module_Id := 43;
-- Width change: truncate or extend. Sign is know in order to possibly
-- detect loss of value.
Id_Utrunc : constant Module_Id := 46;
Id_Strunc : constant Module_Id := 47;
Id_Uextend : constant Module_Id := 48;
Id_Sextend : constant Module_Id := 49;
subtype Truncate_Module_Id is Module_Id range Id_Utrunc .. Id_Strunc;
subtype Extend_Module_Id is Module_Id range Id_Uextend .. Id_Sextend;
-- Extract a bit or a slice at a constant offset.
-- OUT := IN0[OFF+WD-1:OFF]
Id_Extract : constant Module_Id := 50;
-- OUT := IN0[IN1*STEP+OFF+WD-1:IN1*STEP+OFF]
Id_Dyn_Extract : constant Module_Id := 51;
-- This gate has two inputs I, V and one parameter POS.
-- It replaces bits POS + width(V) - 1 .. POS of I by V, ie:
-- T := I;
-- T [POS+width(V)-1:POS] := V
-- OUT := T.
Id_Insert : constant Module_Id := 52;
-- Like Insert but for dynamic values.
-- T := IN0
-- T [IN2*STEP+OFF+WD-1:IN2*STEP+OFF] := IN1
-- OUT := T
Id_Dyn_Insert : constant Module_Id := 53;
-- Positive/rising edge detector. This is a pseudo gate.
-- A negative edge detector can be made using by negating the clock before
-- the detector.
Id_Edge : constant Module_Id := 55;
-- Input signal must always be true.
Id_Assert : constant Module_Id := 56;
Id_Assume : constant Module_Id := 57;
-- Constants are gates with only one constant output. There are multiple
-- kind of constant gates: for small width, the value is stored as a
-- parameter, possibly signed or unsigned extended. For large width
-- (> 128), the value is stored in a table.
Id_Const_UB32 : constant Module_Id := 64;
Id_Const_SB32 : constant Module_Id := 65;
Id_Const_UB64 : constant Module_Id := 66;
Id_Const_SB64 : constant Module_Id := 67;
Id_Const_UB128 : constant Module_Id := 68;
Id_Const_SB128 : constant Module_Id := 69;
Id_Const_UL32 : constant Module_Id := 70;
Id_Const_SL32 : constant Module_Id := 71;
Id_Const_Z : constant Module_Id := 72;
Id_Const_0 : constant Module_Id := 73;
-- Concatenation with N inputs.
Id_Concatn : constant Module_Id := 80;
end Netlists.Gates;
|
