1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
|
# =============================================================================
# ____ _ _ ____ _ _
# _ __ _ _ / ___| | | | _ \| | __| | ___ _ __ ___
# | '_ \| | | | | _| |_| | | | | | / _` |/ _ \| '_ ` _ \
# | |_) | |_| | |_| | _ | |_| | |___ | (_| | (_) | | | | | |
# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
# |_| |___/
# =============================================================================
# Authors:
# Patrick Lehmann
#
# Package module: DOM: Interface items (e.g. generic or port)
#
# License:
# ============================================================================
# Copyright (C) 2019-2021 Tristan Gingold
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <gnu.org/licenses>.
#
# SPDX-License-Identifier: GPL-2.0-or-later
# ============================================================================
from pydecor import export
from pyVHDLModel.VHDLModel import \
InverseExpression as VHDLModel_InverseExpression, \
IdentityExpression as VHDLModel_IdentityExpression, \
NegationExpression as VHDLModel_NegationExpression, \
AbsoluteExpression as VHDLModel_AbsoluteExpression, \
TypeConversion as VHDLModel_TypeConversion, \
FunctionCall as VHDLModel_FunctionCall, \
QualifiedExpression as VHDLModel_QualifiedExpression, \
AdditionExpression as VHDLModel_AdditionExpression, \
SubtractionExpression as VHDLModel_SubtractionExpression, \
ConcatenationExpression as VHDLModel_ConcatenationExpression, \
MultiplyExpression as VHDLModel_MultiplyExpression, \
DivisionExpression as VHDLModel_DivisionExpression, \
RemainderExpression as VHDLModel_RemainderExpression, \
ModuloExpression as VHDLModel_ModuloExpression, \
ExponentiationExpression as VHDLModel_ExponentiationExpression, \
AndExpression as VHDLModel_AndExpression, \
NandExpression as VHDLModel_NandExpression, \
OrExpression as VHDLModel_OrExpression, \
NorExpression as VHDLModel_NorExpression, \
XorExpression as VHDLModel_XorExpression, \
XnorExpression as VHDLModel_XnorExpression, \
EqualExpression as VHDLModel_EqualExpression, \
UnequalExpression as VHDLModel_UnequalExpression, \
GreaterThanExpression as VHDLModel_GreaterThanExpression, \
GreaterEqualExpression as VHDLModel_GreaterEqualExpression, \
LessThanExpression as VHDLModel_LessThanExpression, \
ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression, \
ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression, \
ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression, \
ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression, \
RotateRightExpression as VHDLModel_RotateRightExpression, \
RotateLeftExpression as VHDLModel_RotateLeftExpression, \
Expression
__all__ = []
@export
class InverseExpression(VHDLModel_InverseExpression):
def __init__(self, operand: Expression):
super().__init__()
self._operand = operand
@export
class IdentityExpression(VHDLModel_IdentityExpression):
def __init__(self, operand: Expression):
super().__init__()
self._operand = operand
@export
class NegationExpression(VHDLModel_NegationExpression):
def __init__(self, operand: Expression):
super().__init__()
self._operand = operand
@export
class AbsoluteExpression(VHDLModel_AbsoluteExpression):
def __init__(self, operand: Expression):
super().__init__()
self._operand = operand
@export
class TypeConversion(VHDLModel_TypeConversion):
def __init__(self, operand: Expression):
super().__init__()
self._operand = operand
@export
class FunctionCall(VHDLModel_FunctionCall):
def __init__(self, operand: Expression):
super().__init__()
self._operand = operand
@export
class QualifiedExpression(VHDLModel_QualifiedExpression):
def __init__(self, operand: Expression):
super().__init__()
self._operand = operand
@export
class AdditionExpression(VHDLModel_AdditionExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class SubtractionExpression(VHDLModel_SubtractionExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class ConcatenationExpression(VHDLModel_ConcatenationExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class MultiplyExpression(VHDLModel_MultiplyExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class DivisionExpression(VHDLModel_DivisionExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class RemainderExpression(VHDLModel_RemainderExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class ModuloExpression(VHDLModel_ModuloExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class ExponentiationExpression(VHDLModel_ExponentiationExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class AndExpression(VHDLModel_AndExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class NandExpression(VHDLModel_NandExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class OrExpression(VHDLModel_OrExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class NorExpression(VHDLModel_NorExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class XorExpression(VHDLModel_XorExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class XnorExpression(VHDLModel_XnorExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class EqualExpression(VHDLModel_EqualExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class UnequalExpression(VHDLModel_UnequalExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class GreaterThanExpression(VHDLModel_GreaterThanExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class GreaterEqualExpression(VHDLModel_GreaterEqualExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class LessThanExpression(VHDLModel_LessThanExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class ShiftRightLogicExpression(VHDLModel_ShiftRightLogicExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class ShiftLeftLogicExpression(VHDLModel_ShiftLeftLogicExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class ShiftRightArithmeticExpression(VHDLModel_ShiftRightArithmeticExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class ShiftLeftArithmeticExpression(VHDLModel_ShiftLeftArithmeticExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class RotateRightExpression(VHDLModel_RotateRightExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
@export
class RotateLeftExpression(VHDLModel_RotateLeftExpression):
def __init__(self, left: Expression, right: Expression):
super().__init__()
self._leftOperand = left
self._rightOperand = right
|
