entity t5 is end t5; library ieee; use ieee.std_logic_1164.all; architecture behav of t5 is signal s : std_logic := '0'; begin b: block port (p : out std_logic := 'Z'); port map (p => s); begin end block; b2: block port (p : out std_logic := '1'); port map (p => s); begin end block; process begin wait for 1 ns; assert s = 'X' severity failure; wait; end process; end behav; ' href='ssh://git@git.panaceas.org/git/iCE40/ghdl' title='iCE40/ghdl Git repository'/>
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