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* trans-chap8: Fix individual assocs of signal parametersTristan Gingold2023-02-081-22/+44
* simul: handle signal assignment to procedure individual associationsTristan Gingold2023-02-081-8/+19
* trans-chap8: minor reindentationTristan Gingold2023-02-081-1/+1
* synth: use same layout for records in memory as translateTristan Gingold2023-02-0810-70/+229
* vhdl-canon: remove signal parameters for all-sensitized processes.Tristan Gingold2023-02-084-9/+54
* synth: preliminary work to compute access bounds sizeTristan Gingold2023-02-053-2/+128
* elab-vhdl_objtypes: rename acc_bnd_sz to acc_type_szTristan Gingold2023-02-053-7/+7
* vhdl-prints: improve output of generate statementsTristan Gingold2023-02-041-12/+5
* translate: add --no-elaboration flagTristan Gingold2023-02-045-2/+10
* elab-vhdl_debug: handle package in subprogramsTristan Gingold2023-02-041-0/+13
* simul: refactoring, expose more subprogramsTristan Gingold2023-02-043-35/+47
* mcode/ortho_jit.adb: add option --be-gTristan Gingold2023-02-041-1/+1
* vhdl-sem_decls: fix a regression on subtype indication. Fix #2336Tristan Gingold2023-02-031-1/+1
* vhdl: reduce use of is_anonymous_type_definitionTristan Gingold2023-02-036-34/+40
* TBMTristan Gingold2023-02-024-12/+56
* translate: improve support for Flag_ElaborationTristan Gingold2023-02-022-2/+10
* vhdl: avoid error storms in assertionsTristan Gingold2023-02-022-2/+4
* trans-chap3: minor rewriteTristan Gingold2023-02-021-1/+1
* translate: rework translate_object_subtype_indication.Tristan Gingold2023-02-025-66/+83
* psl-build: fix fusion with epsilon. Fix #2336Tristan Gingold2023-01-311-0/+1
* translate: add a flag to disable elaborationTristan Gingold2023-01-313-106/+125
* elab-debugger: also pass top instance on break_timeTristan Gingold2023-01-313-4/+4
* ghdlsimul: extract simul-main from simul-vhdl_simulTristan Gingold2023-01-316-110/+186
* vhdl-prints: minor rewriteTristan Gingold2023-01-311-31/+33
* PSL: optimize True for goto_repeatTristan Gingold2023-01-311-5/+17
* psl-disp_nfas: add Dump_NFATristan Gingold2023-01-312-0/+57
* synth: avoid a crash after errors in declarations. Fix #2334Tristan Gingold2023-01-301-18/+28
* synth: also fix crash for #2333Tristan Gingold2023-01-301-2/+4
* simul-vhdl_elab: fix computation of nbr of sourcesTristan Gingold2023-01-301-2/+7
* simul: use same packing order for nets and for values.Tristan Gingold2023-01-306-40/+72
* elab-debugger: improve current context for print commandTristan Gingold2023-01-303-6/+17
* elab-vhdl_debug: avoid a crash for lhTristan Gingold2023-01-301-0/+3
* translation.adb: avoid a crash on unused resolver. Fix #2333Tristan Gingold2023-01-301-5/+3
* simul: improve info sig and info timeTristan Gingold2023-01-301-52/+78
* netlists-rename: add commentsTristan Gingold2023-01-301-0/+2
* synth: represent access types as pointers in memoryTristan Gingold2023-01-2913-60/+125
* synth: simplify New_Sname_Artificial (prefix is not used)Tristan Gingold2023-01-294-78/+72
* elab-vhdl_annotations: refactoringTristan Gingold2023-01-292-35/+10
* vhdl: add Is_Owned_Subtype_IndicationTristan Gingold2023-01-293-21/+43
* synth: avoid a crash on subtype indication. Fix #2330Tristan Gingold2023-01-291-1/+1
* synth: handle bit reduction operators. Fix #2328Tristan Gingold2023-01-291-7/+14
* vhdl/trans: support suspend statesTristan Gingold2023-01-2810-16/+56
* vhdl-sem_decls: do not reassign type declarator on subtype aliasesTristan Gingold2023-01-281-13/+19
* synth: improve support of interface typeTristan Gingold2023-01-282-30/+82
* elab-vhdl_annotations: remove useless codeTristan Gingold2023-01-281-18/+0
* vhdl: minor changes to avoid recomputationTristan Gingold2023-01-282-1/+1
* vhdl-evaluation: factorize codeTristan Gingold2023-01-281-108/+94
* synth-vhdl_eval: minor reformattingTristan Gingold2023-01-281-18/+18
* synth: fix incorrect check in array subtype indicationsTristan Gingold2023-01-281-2/+8
* synth-vhdl_oper: add bit-vect and vect-bit operations.Tristan Gingold2023-01-271-12/+24
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 20:37:08 +0000