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* synth: refactoring to reduce global variables.Tristan Gingold2019-09-196-28/+46
* synth: synth_instance_type is now limited.Tristan Gingold2019-09-191-6/+2
* synth: make synth_instance_type private.Tristan Gingold2019-09-197-81/+160
* synth: handle unconnected out ports.Tristan Gingold2019-09-191-5/+8
* synth: handle record subtypes.Tristan Gingold2019-09-193-42/+59
* synth: Add support for PSL cover directive (#930)T. Meissner2019-09-196-3/+49
* synth: improve locations tracking.Tristan Gingold2019-09-188-7/+84
* vhdl: add exit/next flags.Tristan Gingold2019-09-185-63/+173
* synth: remove value_mux2.Tristan Gingold2019-09-185-55/+32
* synth: fix to get_current_assign_value.Tristan Gingold2019-09-171-7/+4
* netlists-dump: add width on extract output.Tristan Gingold2019-09-171-5/+14
* synth: add debug flag -dc to not clean.Tristan Gingold2019-09-173-1/+9
* synth-inference: detect false loop.Tristan Gingold2019-09-176-2/+335
* synth: fold addition on constant nets.Tristan Gingold2019-09-1710-49/+178
* synth: add synth-flags, add debug option -di.Tristan Gingold2019-09-173-1/+32
* synth: minor refactoring about const gates.Tristan Gingold2019-09-154-40/+41
* synth-oper: add support of std_matchTristan Gingold2019-09-151-0/+94
* synth-disp_vhdl: improve support of boolean, suv.Tristan Gingold2019-09-151-17/+16
* synth: add build2_const_vecTristan Gingold2019-09-152-0/+27
* synth-stmts: fix uninitialized variable.Tristan Gingold2019-09-131-1/+9
* synth: initialize subprogram variables.Tristan Gingold2019-09-134-8/+14
* synth: remove get_width from synth-exprTristan Gingold2019-09-123-15/+2
* synth: extract synth-oper from synth-exprTristan Gingold2019-09-126-927/+1012
* synth: handle simple_aggregate.Tristan Gingold2019-09-121-0/+41
* synth: allow empty string literal.Tristan Gingold2019-09-122-2/+4
* vhdl-nodes: add a comment.Tristan Gingold2019-09-121-1/+1
* synth: handle unsigned shift rightTristan Gingold2019-09-111-0/+7
* vhdl-ieee-numeric: recognize shift_right.Tristan Gingold2019-09-111-17/+31
* synth: handle unsigned shift left.Tristan Gingold2019-09-115-107/+163
* synth: add synth_compare_sgn_sgnTristan Gingold2019-09-111-0/+23
* synth: handle constant bit compare.Tristan Gingold2019-09-111-0/+6
* synth: handle numeric_std.resize for signed.Tristan Gingold2019-09-111-0/+15
* synth: improve support of return statement.Tristan Gingold2019-09-118-21/+117
* synth: improve support of negative integer values.Tristan Gingold2019-09-112-15/+29
* synth: add const_x gate.Tristan Gingold2019-09-114-1/+27
* synth: introduce Seq_Context.Tristan Gingold2019-09-112-68/+87
* synth: move synth_user_function_call to synth-stmts.Tristan Gingold2019-09-113-60/+62
* synth: improve support of slices.Tristan Gingold2019-09-111-50/+54
* synth: introduce slice type.Tristan Gingold2019-09-114-1/+26
* synth: Add width field in type_type record.Tristan Gingold2019-09-116-109/+119
* synth: handle alias (WIP, read only).Tristan Gingold2019-09-117-12/+86
* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-114-3/+31
* synth: add const_sb32, add smul/umul.Tristan Gingold2019-09-076-13/+105
* vhdl: recognize numeric_std mul.Tristan Gingold2019-09-072-0/+27
* synth: handle partial assignments in case statements.Tristan Gingold2019-09-073-44/+95
* synth-expr: fix regression of issue 7Tristan Gingold2019-09-061-1/+2
* synth: abstract of Merge_Assigns.Tristan Gingold2019-09-061-56/+111
* vhdl: fix unused warning on protected variable.Tristan Gingold2019-09-061-0/+1
* vhdl: handle P32 in connect_scalar. Fix #918Tristan Gingold2019-09-051-1/+2
* synth: handle const record aggregates.Tristan Gingold2019-09-054-21/+64
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