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* simul: handle concurrent procedure calls (WIP)Tristan Gingold2022-08-211-15/+95
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* simul: handle after clauses in signal assignmentTristan Gingold2022-08-213-70/+111
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* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-204-34/+289
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* elab-vhdl_expr: factorize codeTristan Gingold2022-08-1910-998/+50
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* simul-vhdl_debug: display connectionsTristan Gingold2022-08-191-5/+63
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* simul: handle resolved signals (WIP)Tristan Gingold2022-08-194-49/+332
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* ghdlsimul: add an option to debug before elaborationTristan Gingold2022-08-183-3/+6
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* simul: handle individual associationsTristan Gingold2022-08-172-4/+16
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* simul: add create_connectsTristan Gingold2022-08-174-46/+144
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* simul: create terminals (WIP)Tristan Gingold2022-08-174-8/+62
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* elab-vhdl_objtypes: handle holes in comparisons.Tristan Gingold2022-08-161-7/+72
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* netlists-memories: add a TODO commentTristan Gingold2022-08-161-0/+8
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* synth/netlists: add commentsTristan Gingold2022-08-162-7/+14
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* synth-vhdl_expr: optimize record with one element.Tristan Gingold2022-08-161-3/+3
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* netlists-memories: renaming and add commentsTristan Gingold2022-08-161-25/+38
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* psl-rewrites: minor style changeTristan Gingold2022-08-161-2/+1
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* vhdl-prints: improve handling of PSL. For #2178Tristan Gingold2022-08-156-63/+184
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* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-1513-226/+292
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* elab-vhdl_values-debug: improve output of debug_valtypTristan Gingold2022-08-141-1/+3
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* synth-vhdl_context: fix handling of alias in get_net. Fix #2177Tristan Gingold2022-08-141-4/+3
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* vhdl: recognize log10 and sqrt from math_real. Fix #2176Tristan Gingold2022-08-144-10/+32
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* synth: handle assignment to record aggregateTristan Gingold2022-08-142-31/+109
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* netlists-memories: improve checks to avoid the crash of #2077Tristan Gingold2022-08-141-32/+75
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* netlists-memories: fix a crash on multi-dim memories. For #2077Tristan Gingold2022-08-131-3/+6
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* trans-chap3: fix invalid copy of element layout. For #2166Tristan Gingold2022-08-121-2/+4
| | | | Build element layout of a subtype if the element was defined by the subtype.
* vhdl: add support for file subtype. Fix #2174Tristan Gingold2022-08-1112-262/+329
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* vhdl-sem_stmts: handle external signal names in force assign. Fix #2173Tristan Gingold2022-08-111-1/+5
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* vhdl-parse.adb: parse pathname expressionTristan Gingold2022-08-111-0/+10
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* vhdl-sem_stmts.adb: handle signal assignment to external names. Fix #2172Tristan Gingold2022-08-111-0/+4
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* vhdl-sem_expr: fix a crash on invalid aggregate. Fix #2131Tristan Gingold2022-08-111-15/+30
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* trans-chap5: handle inertial individual association. Fix #2118Tristan Gingold2022-08-111-13/+20
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* vhdl-sem_expr: add an error message for unbounded element aggregate.Tristan Gingold2022-08-111-7/+12
| | | | | | But also propagate bounds on qualified expressions. Fix #2112
* trans-chap7: handle concat of unbounded elements. Fix #2055Tristan Gingold2022-08-111-33/+58
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* vhdl-sem_names: factorize code for element attributeTristan Gingold2022-08-101-56/+10
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* trans: rework aggregate. For #2166Tristan Gingold2022-08-103-58/+65
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* vhdl: add Determined_Aggregate_Flag field. For #2166Tristan Gingold2022-08-105-134/+177
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* synth-vhdl_oper.adb: fix mul uns uns. Fix #2169Tristan Gingold2022-08-101-1/+1
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* vhdl: add an owner to interface type definitionTristan Gingold2022-08-076-187/+233
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* vhdl-sem_names.adb(are_types_closely_related): handle vhdl08 definitionTristan Gingold2022-08-071-14/+24
| | | | Fix #2155
* vhdl-sem.adb: lexical conformance is now a relaxed error. Fix #2165Tristan Gingold2022-08-072-2/+7
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* vhdl-sem.adb(are_trees_equal): handle qualified expressions. Fix #2164Tristan Gingold2022-08-071-1/+2
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* vhdl-sem_assocs: add commentsTristan Gingold2022-08-071-0/+7
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* vhdl-prints: handle default in interface subprogramTristan Gingold2022-08-071-1/+19
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* vhdl: add support for default in interface subprogram. Fix #2163Tristan Gingold2022-08-0712-419/+649
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* PSL: Add handling of N_HDL_Bool to Dump_Expr procedure (#2158)T. Meissner2022-08-041-1/+2
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* synth-vhdl_oper: remove check for positive rotation amount. Fix #2159Tristan Gingold2022-08-041-3/+1
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* vhdl-prints.adb: avoid crash on PSL endpointsTristan Gingold2022-08-041-3/+12
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* trans-chap9.adb: destroy types in PSL expressions. For #2157Tristan Gingold2022-08-041-3/+31
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* vhdl-prints: improve outputTristan Gingold2022-08-032-2/+23
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* psl-build.adb: disable incorrect optimization. Fix #2157Tristan Gingold2022-08-032-2/+5
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