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Age
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*
vhdl-sem_names.adb(are_types_closely_related): handle vhdl08 definition
Tristan Gingold
2022-08-07
1
-14
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+24
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Fix #2155
*
vhdl-sem.adb: lexical conformance is now a relaxed error. Fix #2165
Tristan Gingold
2022-08-07
2
-2
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+7
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*
vhdl-sem.adb(are_trees_equal): handle qualified expressions. Fix #2164
Tristan Gingold
2022-08-07
1
-1
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+2
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*
vhdl-sem_assocs: add comments
Tristan Gingold
2022-08-07
1
-0
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+7
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*
vhdl-prints: handle default in interface subprogram
Tristan Gingold
2022-08-07
1
-1
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+19
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*
vhdl: add support for default in interface subprogram. Fix #2163
Tristan Gingold
2022-08-07
12
-419
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+649
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*
PSL: Add handling of N_HDL_Bool to Dump_Expr procedure (#2158)
T. Meissner
2022-08-04
1
-1
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+2
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*
synth-vhdl_oper: remove check for positive rotation amount. Fix #2159
Tristan Gingold
2022-08-04
1
-3
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+1
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vhdl-prints.adb: avoid crash on PSL endpoints
Tristan Gingold
2022-08-04
1
-3
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+12
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*
trans-chap9.adb: destroy types in PSL expressions. For #2157
Tristan Gingold
2022-08-04
1
-3
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+31
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*
vhdl-prints: improve output
Tristan Gingold
2022-08-03
2
-2
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+23
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*
psl-build.adb: disable incorrect optimization. Fix #2157
Tristan Gingold
2022-08-03
2
-2
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+5
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*
trans-chap3: translate subtype indication of access subtype. Fix #2152
Tristan Gingold
2022-07-30
1
-3
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+14
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*
psl-nodes: add comments
Tristan Gingold
2022-07-30
1
-0
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+2
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*
psl-rewrites.adb: fix inclusive before. Fix #2153
Tristan Gingold
2022-07-29
1
-1
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+3
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*
vhdl-sem_stmts: set stop_flag on call to stop and severity failure.
Tristan Gingold
2022-07-29
1
-22
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+56
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Fix #2150
*
vhdl-nodes: add Get/Set_Stop_Flag. For #2150
Tristan Gingold
2022-07-29
4
-116
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+164
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*
netlists-memories: allow X in memories. Fix #2146
Tristan Gingold
2022-07-29
1
-2
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+4
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*
netlists-disp_verilog(disp_const_log): fix output. Fix #2149
Tristan Gingold
2022-07-28
1
-2
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+2
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*
synth-disp_vhdl: fix out conversion. Fix #2145
Tristan Gingold
2022-07-28
1
-21
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+29
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In the case the width of a vector is only 1 bit
*
vhdl: check read for attribute parameter and aggregates. Fix #2148
Tristan Gingold
2022-07-28
2
-3
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+20
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*
vhdl-sem_names: add implicit function call for array attributes. Fix #2147
Tristan Gingold
2022-07-28
1
-40
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+8
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options.adb: -Werror=X enables warning X.
Tristan Gingold
2022-07-28
1
-0
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+1
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*
synth-vhdl_expr: add support for branch quantities
Tristan Gingold
2022-07-28
2
-0
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+2
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*
simul-vhdl_simul: add scalar terminal table
Tristan Gingold
2022-07-28
1
-0
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+16
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*
simul-vhdl_debug: add info terminal
Tristan Gingold
2022-07-28
1
-20
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+69
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*
vhdl-sem_names: allow element attribute on element attribute. Fix #2141
Tristan Gingold
2022-07-28
4
-17
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+34
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*
elab-vhdl_expr: fix handling of multi-dim arrays. Fix #2144
Tristan Gingold
2022-07-27
1
-9
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+17
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*
synth-disp_vhdl: improve output for unsigned. Fix #2139
Tristan Gingold
2022-07-27
1
-2
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+17
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*
elab-vhdl_expr: fix incorrect type of multi-dim array indexing during elab
Tristan Gingold
2022-07-27
1
-0
/
+9
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Fix #2143
*
synthesis.adb: cleanup after expand. For #2142
Tristan Gingold
2022-07-27
1
-0
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+2
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*
netlists-disp_vhdl: adjust output for #2140
Tristan Gingold
2022-07-27
1
-2
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+8
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*
netlists-expands: do not try to clean input of dyn_extract. Fix #2142
Tristan Gingold
2022-07-27
1
-5
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+1
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*
netlist-disp_vhdl: add a separator between instances and signals.
Tristan Gingold
2022-07-26
1
-1
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+1
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Fix #2140
*
vhdl-parse: set reference_terminal flag
Tristan Gingold
2022-07-26
1
-0
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+1
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*
vhdl-canon: handle conditional variable assignment. Fix #2138
Tristan Gingold
2022-07-25
1
-1
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+16
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*
simul: gather terminals
Tristan Gingold
2022-07-25
4
-3
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+74
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*
synth/elab-vhdl_values: add Value_Terminal
Tristan Gingold
2022-07-25
6
-4
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+38
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*
vhdl-nodes: add Get/Set_Reference_Terminal_Flag
Tristan Gingold
2022-07-25
4
-204
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+247
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*
synth-environment: fix memory crash. Fix #2139
Tristan Gingold
2022-07-25
1
-2
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+8
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*
dyn_tables,tables: add Reserve. For #2139
Tristan Gingold
2022-07-25
4
-5
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+28
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*
src/simul: rewrite of ghdl/simul based on synth
Tristan Gingold
2022-07-24
7
-0
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+3759
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*
synth: add hook for dot attribute
Tristan Gingold
2022-07-24
3
-7
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+17
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*
vhdl: handle element attribute in declarations. Fix #2136
Tristan Gingold
2022-07-21
2
-12
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+23
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*
elab-vhdl_decls: elaborate dot attribute
Tristan Gingold
2022-07-21
3
-4
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+14
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*
vhdl-nodes: renaming.
Tristan Gingold
2022-07-21
21
-128
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+130
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Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
*
elab-vhdl_decls: elaborate implicit signals
Tristan Gingold
2022-07-21
1
-2
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+23
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*
Makefile.in: allow build of ghdl_mcode with sundials enabled
Tristan Gingold
2022-07-21
1
-0
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+25
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*
synth-vhdl_expr: add hook for quantities
Tristan Gingold
2022-07-20
2
-11
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+23
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*
elab-vhdl_debug: handle signals in packages
Tristan Gingold
2022-07-20
1
-2
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+8
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