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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-28 19:29:57 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-28 19:29:57 +0200 |
| commit | 06e60468d4ca8d964362768280c2ed2e83e5d1a8 (patch) | |
| tree | 3a9a50a8f3ab70d7a4e580c72ca62fad4e860884 /src | |
| parent | 82520ebf749bf22a52f9065f6af77ea676e16a5f (diff) | |
| download | ghdl-06e60468d4ca8d964362768280c2ed2e83e5d1a8.tar.gz ghdl-06e60468d4ca8d964362768280c2ed2e83e5d1a8.tar.bz2 ghdl-06e60468d4ca8d964362768280c2ed2e83e5d1a8.zip | |
netlists-disp_verilog(disp_const_log): fix output. Fix #2149
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 133959e5f..1ab834fe9 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -301,7 +301,8 @@ package body Netlists.Disp_Verilog is Nd : constant Width := W / 32; Ld : constant Natural := Natural (W mod 32); begin - Put ('"'); + Put_Uns32 (W); + Put ("'b"); if Ld > 0 then Disp_Binary_Digits (Get_Param_Uns32 (Inst, Param_Idx (2 * Nd)), Get_Param_Uns32 (Inst, Param_Idx (2 * Nd + 1)), @@ -313,7 +314,6 @@ package body Netlists.Disp_Verilog is Get_Param_Uns32 (Inst, Param_Idx (2 * (I - 1)) + 1), 32); end loop; - Put ('"'); end Disp_Const_Log; procedure Disp_X_Lit (W : Width; C : Character) is |