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* grt: add analog_solver (work in progress)Tristan Gingold2022-07-204-9/+197
* grt: add real now variable.Tristan Gingold2022-07-204-0/+19
* ghdlsimul: simplify elaboration circuiteryTristan Gingold2022-07-201-13/+0
* elab-vhdl_context: add iterator for top-level packagesTristan Gingold2022-07-202-0/+36
* configure: add --with-sundials (preliminary work)Tristan Gingold2022-07-202-0/+44
* elab-vhdl_debug: disp fp64 valuesTristan Gingold2022-07-204-2/+10
* vhdl-sem_specs: allow protected body in scope of an attribute. Fix #2134Tristan Gingold2022-07-161-0/+2
* vhdl: preliminary work to elaborat quantitiesTristan Gingold2022-07-167-2/+26
* elab-vhdl_values: add Create_Value_QuantityTristan Gingold2022-07-166-2/+41
* grt-types: add Mode_AboveTristan Gingold2022-07-164-7/+15
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-164-18/+26
* vhdl-cannon: add Canon_Extract_Sensitivity_Break_StatementTristan Gingold2022-07-162-1/+16
* netlists-inference: add (disabled) code to add a latchTristan Gingold2022-07-161-26/+103
* synth: Display dlatchTristan Gingold2022-07-143-2/+9
* netlists: add d-latchTristan Gingold2022-07-123-2/+38
* Fix access check failed from iir_kind_selected_element (#2132)Michael Nolan2022-07-121-0/+1
* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-113-4/+13
* netlists-inference: detect false loops only for variables. Fix #2125Tristan Gingold2022-07-111-2/+3
* netlists-disp_verilog: do not connect to null-range output. For #2113Tristan Gingold2022-07-081-41/+47
* vhdl-evaluation: explicitly compute integer_exp to handle overflow.Tristan Gingold2022-07-071-2/+31
* vhdl-evaluation: make overflow_literal non locally static.Tristan Gingold2022-07-072-1/+6
* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
* Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-051-1/+3
* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
* netlists-disp_verilog: handle Id_Abs. Fix #2113Tristan Gingold2022-07-041-1/+1
* synth-vhdl_insts: also handled unbounded records in hash names.Tristan Gingold2022-07-021-0/+7
* vhdl-sem_psl: analyze strong propertiesTristan Gingold2022-07-021-1/+2
* vhdl-sem_names: avoid crash on incorrect selected name.Tristan Gingold2022-07-021-6/+6
* vhdl-sem_decls: avoid crash on self use of a generic package.Tristan Gingold2022-07-021-0/+10
* vhdl: avoid crash on incorrect use of attributes.Tristan Gingold2022-07-025-14/+40
* vhdl: avoid crash on incorrect use of signaturesTristan Gingold2022-07-023-281/+292
* vhdl-evaluation: handle more operations (thought synth).Tristan Gingold2022-07-021-2/+1
* vhdl-sem_names: avoid duplicate error message. For #2100Tristan Gingold2022-06-281-1/+19
* netlists-disp_verilog: adjust, discard null signals. For #2113Tristan Gingold2022-06-281-1/+6
* netlists-disp_verilog: fix warningTristan Gingold2022-06-271-1/+2
* synth/netlists-disp_verilog: skip null input port. Fix #2113Tristan Gingold2022-06-271-15/+20
* synth: rework #2109 - remove null wiresTristan Gingold2022-06-278-26/+87
* synth/netlists-disp_verilog: adjust previous patch. For #2109Tristan Gingold2022-06-271-1/+2
* netlists-disp_verilog: do not display ports of width 0. Fix #2109Tristan Gingold2022-06-271-5/+19
* Fix nested commentssudden62022-06-261-41/+41
* vhdl-parse: fix crashes after error. Fix #2110Tristan Gingold2022-06-261-2/+6
* vhdl-parse_psl: avoid crash on error. For #2110Tristan Gingold2022-06-261-1/+7
* trans-chap8: adjust conditions to pass parameters. Fix #2104Tristan Gingold2022-06-221-2/+9
* vhdl-sem.adb: avoid a crash on conformance error. Fix #2103Tristan Gingold2022-06-211-2/+2
* vhdl-sem_lib: do not disable warnings for files in -c/-rTristan Gingold2022-06-191-1/+5
* trans-chap7: translate anonymous subtype of overflow literal. Fox #2066Tristan Gingold2022-06-191-2/+6
* vhdl-sem_expr: check expression index range for aggregate. Fix #2066Tristan Gingold2022-06-191-0/+25
* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-162-4/+13
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