iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	synth: handle open entity aspect	Tristan Gingold	2022-09-07	1	-4/+4
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*	elab-vhdl_heap: fix handling of simple access types	Tristan Gingold	2022-09-07	1	-4/+17
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*	simul: fix computation for number of drivers	Tristan Gingold	2022-09-06	1	-1/+2
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*	synth: handle generics in blocks	Tristan Gingold	2022-09-06	4	-10/+53
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*	simul: add an hook to display report/assert message	Tristan Gingold	2022-09-06	3	-50/+128
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*	synth-vhdl_eval: handle std_logic_signed and std_logic_unsigned	Tristan Gingold	2022-09-06	1	-55/+111
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*	synth: add evaluation for ieee.std_logic_arith	Tristan Gingold	2022-09-05	6	-43/+1181
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*	grt: add a SIGFPE handler for linux x86/64. Fix #2185	Tristan Gingold	2022-09-02	1	-0/+4
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*	synth: extract synth-ieee-utils from synth-ieee-numeric_std	Tristan Gingold	2022-09-02	2	-21/+46
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*	synth: improve debug subprograms	Tristan Gingold	2022-09-02	2	-1/+8
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*	synth: use areapools	Tristan Gingold	2022-09-02	30	-269/+981
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*	synth: factorize code for tracing statements execution	Tristan Gingold	2022-09-02	4	-16/+23
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*	simul: detect multiple drivers for unresolved signals	Tristan Gingold	2022-09-02	1	-8/+93
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*	simul-vhdl_simul: simplify procedure connect	Tristan Gingold	2022-08-26	1	-41/+22
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*	vhdl-sem_assocs: improve error message	Tristan Gingold	2022-08-25	1	-1/+1
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*	synth: handle component aspect configuration	Tristan Gingold	2022-08-25	1	-1/+5
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*	simul: handle connections of records	Tristan Gingold	2022-08-25	1	-1/+18
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*	synth: handle indexes/ranges in configurations for generate blocks	Tristan Gingold	2022-08-25	2	-5/+30
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*	synth: handle unbounded top-level ports	Tristan Gingold	2022-08-25	1	-9/+18
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*	synth: handle type left/right attributes	Tristan Gingold	2022-08-25	3	-0/+26
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*	simul: improve support of float signals	Tristan Gingold	2022-08-24	1	-3/+7
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*	grt-disp_signals: also disp conversions ranges	Tristan Gingold	2022-08-24	1	-0/+11
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*	simul: handle conversions and associations with constants	Tristan Gingold	2022-08-24	2	-70/+399
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*	simul: simplify code	Tristan Gingold	2022-08-23	2	-16/+7
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*	simul: factorize code to compute number of sources	Tristan Gingold	2022-08-23	4	-120/+50
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*	simul-vhdl_debug: disp nbr sources	Tristan Gingold	2022-08-23	1	-1/+15
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*	simul: add extra drivers for ports without sources	Tristan Gingold	2022-08-23	3	-14/+152
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*	elab: add default value to ports	Tristan Gingold	2022-08-23	4	-13/+28
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*	grt-signals: add ghdl_signal_add_extra_driver	Tristan Gingold	2022-08-23	2	-0/+19
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*	grt-signals: internal refactoring for drivers creation	Tristan Gingold	2022-08-22	1	-25/+39
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*	synth-vhdl_static_proc: handle std.env.finish	Tristan Gingold	2022-08-21	1	-1/+2
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*	simul-vhdl_simul: handle waveforms in signal assignments	Tristan Gingold	2022-08-21	2	-40/+51
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*	synth: factorize code for synth_subtype_conversion	Tristan Gingold	2022-08-21	9	-53/+35
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*	grt-errors: remove error_hook (was unused)	Tristan Gingold	2022-08-21	2	-14/+0
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*	simul: rework assertions execution and error handling	Tristan Gingold	2022-08-21	5	-10/+13
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*	simul: handle concurrent procedure calls (WIP)	Tristan Gingold	2022-08-21	1	-15/+95
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*	simul: handle after clauses in signal assignment	Tristan Gingold	2022-08-21	3	-70/+111
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*	simul-vhdl_simul: add support for PSL directives	Tristan Gingold	2022-08-20	4	-34/+289
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*	elab-vhdl_expr: factorize code	Tristan Gingold	2022-08-19	10	-998/+50
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*	simul-vhdl_debug: display connections	Tristan Gingold	2022-08-19	1	-5/+63
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*	simul: handle resolved signals (WIP)	Tristan Gingold	2022-08-19	4	-49/+332
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*	ghdlsimul: add an option to debug before elaboration	Tristan Gingold	2022-08-18	3	-3/+6
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*	simul: handle individual associations	Tristan Gingold	2022-08-17	2	-4/+16
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*	simul: add create_connects	Tristan Gingold	2022-08-17	4	-46/+144
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*	simul: create terminals (WIP)	Tristan Gingold	2022-08-17	4	-8/+62
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*	elab-vhdl_objtypes: handle holes in comparisons.	Tristan Gingold	2022-08-16	1	-7/+72
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*	netlists-memories: add a TODO comment	Tristan Gingold	2022-08-16	1	-0/+8
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*	synth/netlists: add comments	Tristan Gingold	2022-08-16	2	-7/+14
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*	synth-vhdl_expr: optimize record with one element.	Tristan Gingold	2022-08-16	1	-3/+3
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*	netlists-memories: renaming and add comments	Tristan Gingold	2022-08-16	1	-25/+38
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