aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Expand)AuthorAgeFilesLines
...
* synth: handle open entity aspectTristan Gingold2022-09-071-4/+4
* elab-vhdl_heap: fix handling of simple access typesTristan Gingold2022-09-071-4/+17
* simul: fix computation for number of driversTristan Gingold2022-09-061-1/+2
* synth: handle generics in blocksTristan Gingold2022-09-064-10/+53
* simul: add an hook to display report/assert messageTristan Gingold2022-09-063-50/+128
* synth-vhdl_eval: handle std_logic_signed and std_logic_unsignedTristan Gingold2022-09-061-55/+111
* synth: add evaluation for ieee.std_logic_arithTristan Gingold2022-09-056-43/+1181
* grt: add a SIGFPE handler for linux x86/64. Fix #2185Tristan Gingold2022-09-021-0/+4
* synth: extract synth-ieee-utils from synth-ieee-numeric_stdTristan Gingold2022-09-022-21/+46
* synth: improve debug subprogramsTristan Gingold2022-09-022-1/+8
* synth: use areapoolsTristan Gingold2022-09-0230-269/+981
* synth: factorize code for tracing statements executionTristan Gingold2022-09-024-16/+23
* simul: detect multiple drivers for unresolved signalsTristan Gingold2022-09-021-8/+93
* simul-vhdl_simul: simplify procedure connectTristan Gingold2022-08-261-41/+22
* vhdl-sem_assocs: improve error messageTristan Gingold2022-08-251-1/+1
* synth: handle component aspect configurationTristan Gingold2022-08-251-1/+5
* simul: handle connections of recordsTristan Gingold2022-08-251-1/+18
* synth: handle indexes/ranges in configurations for generate blocksTristan Gingold2022-08-252-5/+30
* synth: handle unbounded top-level portsTristan Gingold2022-08-251-9/+18
* synth: handle type left/right attributesTristan Gingold2022-08-253-0/+26
* simul: improve support of float signalsTristan Gingold2022-08-241-3/+7
* grt-disp_signals: also disp conversions rangesTristan Gingold2022-08-241-0/+11
* simul: handle conversions and associations with constantsTristan Gingold2022-08-242-70/+399
* simul: simplify codeTristan Gingold2022-08-232-16/+7
* simul: factorize code to compute number of sourcesTristan Gingold2022-08-234-120/+50
* simul-vhdl_debug: disp nbr sourcesTristan Gingold2022-08-231-1/+15
* simul: add extra drivers for ports without sourcesTristan Gingold2022-08-233-14/+152
* elab: add default value to portsTristan Gingold2022-08-234-13/+28
* grt-signals: add ghdl_signal_add_extra_driverTristan Gingold2022-08-232-0/+19
* grt-signals: internal refactoring for drivers creationTristan Gingold2022-08-221-25/+39
* synth-vhdl_static_proc: handle std.env.finishTristan Gingold2022-08-211-1/+2
* simul-vhdl_simul: handle waveforms in signal assignmentsTristan Gingold2022-08-212-40/+51
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-219-53/+35
* grt-errors: remove error_hook (was unused)Tristan Gingold2022-08-212-14/+0
* simul: rework assertions execution and error handlingTristan Gingold2022-08-215-10/+13
* simul: handle concurrent procedure calls (WIP)Tristan Gingold2022-08-211-15/+95
* simul: handle after clauses in signal assignmentTristan Gingold2022-08-213-70/+111
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-204-34/+289
* elab-vhdl_expr: factorize codeTristan Gingold2022-08-1910-998/+50
* simul-vhdl_debug: display connectionsTristan Gingold2022-08-191-5/+63
* simul: handle resolved signals (WIP)Tristan Gingold2022-08-194-49/+332
* ghdlsimul: add an option to debug before elaborationTristan Gingold2022-08-183-3/+6
* simul: handle individual associationsTristan Gingold2022-08-172-4/+16
* simul: add create_connectsTristan Gingold2022-08-174-46/+144
* simul: create terminals (WIP)Tristan Gingold2022-08-174-8/+62
* elab-vhdl_objtypes: handle holes in comparisons.Tristan Gingold2022-08-161-7/+72
* netlists-memories: add a TODO commentTristan Gingold2022-08-161-0/+8
* synth/netlists: add commentsTristan Gingold2022-08-162-7/+14
* synth-vhdl_expr: optimize record with one element.Tristan Gingold2022-08-161-3/+3
* netlists-memories: renaming and add commentsTristan Gingold2022-08-161-25/+38
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 01:30:12 +0000