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* synth: renaming (synth-static_oper -> synth-vhdl_eval)Tristan Gingold2022-04-274-62/+61
* synth-static_oper: abstract codeTristan Gingold2022-04-271-21/+30
* vhdl-sem_expr: minor renamingTristan Gingold2022-04-271-3/+6
* vhdl-sem_expr: add a commentTristan Gingold2022-04-271-0/+21
* synth-static_oper: handle bit/boolean array element operationsTristan Gingold2022-04-272-3/+29
* vhdl: handle static expressions with ieee operationsTristan Gingold2022-04-262-12/+370
* ghdldrv: call elab.vhdl_objtypes.init in optionsTristan Gingold2022-04-262-3/+3
* synth: abstract code for reuse by evaluationTristan Gingold2022-04-267-52/+78
* synth-static_oper: fully remove dependency on synth_instanceTristan Gingold2022-04-263-39/+44
* synth-static_oper: do not depend on instance for static operations.Tristan Gingold2022-04-267-62/+91
* vhdl: avoid a crash after errors in associations for packagesTristan Gingold2022-04-223-96/+115
* netlists-disp_verilog: output default value for pmux. Fix #2041Tristan Gingold2022-04-211-0/+1
* vhdl-sem_names.adb: avoid a crash on incorrect type markTristan Gingold2022-04-202-1/+12
* ghdldrv: add --all option to dir commandYuni Tsukiyama2022-04-191-3/+61
* trans-chap2.adb: adjust owner_subtype for instantiations. Fix #2026Tristan Gingold2022-04-152-0/+39
* vhdl-sem_names(sem_check_all_sensitized): only consider interface signalTristan Gingold2022-04-152-3/+14
* synth-vhdl_stmts: check subtype compatibility for scalar signal assoc.Tristan Gingold2022-04-153-1/+93
* synth: do not emit a warning for the gclk attribute. Fix #2035Tristan Gingold2022-04-131-1/+2
* synth: handle type declarations in vunit. Fix #2034Tristan Gingold2022-04-135-13/+23
* synth: add support for subtype declaration in vunits. Fix #2033Tristan Gingold2022-04-135-235/+249
* vhdl-sem.adb: adjust location of error message. Fix #2031Tristan Gingold2022-04-111-1/+1
* elab-vhdl_insts: also recurse for instantiations in vunits.Tristan Gingold2022-04-081-74/+93
* synth-vhdl_stmts: emit an error message on missing return. Fix #2019Tristan Gingold2022-04-061-1/+3
* synth-vhdl_insts: also finalize entity declarationsTristan Gingold2022-04-061-0/+1
* synth: do not add info for element subtype (except for arrays).Tristan Gingold2022-04-055-48/+55
* binary_file-coff: fix symbols writeTristan Gingold2022-04-051-29/+58
* ortho/mcode: fix win64 stack alignmentTristan Gingold2022-04-041-1/+1
* ortho/mcode: generate unwind info on win64 (WIP)Tristan Gingold2022-04-043-2/+100
* ortho/mcode: handle image relative relocation (for Win64)Tristan Gingold2022-04-043-4/+29
* ortho/mcode: handle x86-64 coff image dump (WIP)Tristan Gingold2022-04-043-24/+31
* synth: handle individual assoc of unbounded interface. Fix #2023Tristan Gingold2022-04-042-1/+4
* synth: handle shared variable without default value.Tristan Gingold2022-04-042-1/+4
* mcode: improve support of Win64 (prolog)Tristan Gingold2022-04-013-29/+41
* grt-readline.ads: use types from grt-typesTristan Gingold2022-03-301-16/+5
* mcode: improve support of Win64 (allocate stack for home registers)Tristan Gingold2022-03-303-6/+22
* Add chkstk-x64 for windows x64Tristan Gingold2022-03-303-2/+70
* translate: adjust null access check: add an explicit check.Tristan Gingold2022-03-266-31/+66
* trans-chap6: add an explicit memory access during fat access deferenceTristan Gingold2022-03-251-0/+10
* ghdldrv: extract ghdllib from ghdlsynthTristan Gingold2022-03-226-63/+115
* grt: extract grt-vhdl_types from grt-typesTristan Gingold2022-03-2232-139/+195
* synth-vhdl_expr: minor refactoring - add commentsTristan Gingold2022-03-201-16/+34
* synth-vhdl_expr(value2logvec): fix vlen handling. Fix #2013Tristan Gingold2022-03-201-7/+13
* synth-vhdl_context: adjust mask. Fix #2011Tristan Gingold2022-03-181-1/+1
* vhdl-19: analyze return identifierTristan Gingold2022-03-161-0/+18
* Fix include-dir paths returned by cmdline _again_Daniel Gröber2022-03-141-1/+2
* vhdl: check access type restrictions also on completion. Fix #2006Tristan Gingold2022-03-133-25/+32
* Fix hardcoded values in gcc backend's default_pathsDaniel Gröber2022-03-131-44/+0
* netlists-disp_verilog: fix disp_const_bitTristan Gingold2022-03-121-2/+2
* vhdl: check association restrictions for operators. Fix #1999Tristan Gingold2022-03-113-170/+181
* synth: check matching bounds for concatenationTristan Gingold2022-03-112-2/+4
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