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* Regenerate ghdlsynth_gates.hTristan Gingold2019-10-021-19/+24
* netlists-disp_vhdl: display constant signals connected to user submodules.Tristan Gingold2019-10-011-0/+2
* synth: handle string subtype defined by a port. Fix #958Tristan Gingold2019-10-012-7/+20
* synth: fix in extract_merge_partial_assigns.Tristan Gingold2019-10-012-3/+10
* synth-environment-debug: add dump_partial_assign.Tristan Gingold2019-10-011-10/+17
* synth: fix a crash on choice by range for aggregate.Tristan Gingold2019-10-011-1/+2
* synth: add support for integer rem.Tristan Gingold2019-10-014-3/+12
* synth: handle selected element of const record.Tristan Gingold2019-10-011-5/+8
* synth: improve support of arrays or arrays. Fix #955Tristan Gingold2019-10-0110-62/+110
* synth: handle range defined by high/low attributes. Fix #956Tristan Gingold2019-09-301-2/+2
* synth: improve support of * and /. Fix #953Tristan Gingold2019-09-303-2/+46
* vhdl: recognize div operators.Tristan Gingold2019-09-302-0/+27
* synth-oper: implement >= and <= for uns/nat. Fix #952Tristan Gingold2019-09-301-0/+6
* synth-inference: handl 'EXPR and CLK' condition. Fix #951Tristan Gingold2019-09-301-2/+17
* synth-insts: refactoring.Tristan Gingold2019-09-301-40/+32
* synth-insts: create net object for input port. FixTristan Gingold2019-09-301-3/+14
* synth: renaming and minor refactoring.Tristan Gingold2019-09-304-74/+43
* synth: minor refactoring.Tristan Gingold2019-09-301-4/+4
* synth-expr: minor factorisation.Tristan Gingold2019-09-301-25/+19
* vhdl-std_package: reduce cascaded error messages.Tristan Gingold2019-09-301-0/+1
* synth-decls: improve handling of subtype aliases forTristan Gingold2019-09-301-26/+42
* synth: check matching bounds for array equality. Fix #947Tristan Gingold2019-09-303-4/+56
* synth: convert subtype in alias declaration. Fix #946Tristan Gingold2019-09-301-2/+6
* synth: handle alias for is_const. Fix #948Tristan Gingold2019-09-301-2/+3
* synth: handle conversion from slice to unbounded vector.Tristan Gingold2019-09-301-0/+2
* synth: handle while-loop statement.Tristan Gingold2019-09-301-0/+39
* synth: special handling of 'const' functions.Tristan Gingold2019-09-307-16/+134
* synth: slice: avoid crash in case of incorrect slice.Tristan Gingold2019-09-301-4/+4
* synth: refactoring of alias (allow alias of anything).Tristan Gingold2019-09-307-34/+40
* synth: handle slice with index from a record.Tristan Gingold2019-09-301-5/+15
* synth: introduce type_logicTristan Gingold2019-09-296-16/+42
* synth: add support of alias of alias. Fix #945Tristan Gingold2019-09-281-0/+8
* synth: add support for mod operator.Tristan Gingold2019-09-283-24/+30
* netlists-disp_vhdl: improve disp_x_lit.Tristan Gingold2019-09-281-3/+9
* synth-environment: optimize cascaded if.Tristan Gingold2019-09-281-1/+27
* netlists-disp_vhdl: handle id_edge.Tristan Gingold2019-09-281-0/+3
* synth-stmts: simple optimization for loop control logic.Tristan Gingold2019-09-281-10/+19
* synth: disp net number in netlists-dumpTristan Gingold2019-09-281-1/+13
* synth: finalize declarations and free wires.Tristan Gingold2019-09-276-21/+214
* synth: handle range attribute; handle vhdl08 array subtype.Tristan Gingold2019-09-271-19/+25
* synth-environment-debug: improve.Tristan Gingold2019-09-261-1/+2
* synth: handle alias for reshape.Tristan Gingold2019-09-261-0/+2
* synth: do subtype conversion for variable defaultTristan Gingold2019-09-261-0/+2
* synth: do subtype conversion for expression at calls.Tristan Gingold2019-09-262-15/+10
* synth: subtype conversion for selected elements.Tristan Gingold2019-09-261-1/+2
* synth: fix handling of single-bit memories.Tristan Gingold2019-09-262-5/+13
* synth: allow entities with no ports.Tristan Gingold2019-09-251-1/+0
* synth: fix crash on slice of slice.Tristan Gingold2019-09-251-1/+2
* synth-stmts: allow slice as case expression.Tristan Gingold2019-09-251-1/+1
* synth: handle array equality (for constances).Tristan Gingold2019-09-253-1/+22
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