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* synth: Display dlatchTristan Gingold2022-07-143-2/+9
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* netlists: add d-latchTristan Gingold2022-07-123-2/+38
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* Fix access check failed from iir_kind_selected_element (#2132)Michael Nolan2022-07-121-0/+1
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* synth-environment: do inference during wire finalizationTristan Gingold2022-07-111-13/+31
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* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-113-4/+13
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* netlists-inference: detect false loops only for variables. Fix #2125Tristan Gingold2022-07-111-2/+3
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* netlists-disp_verilog: do not connect to null-range output. For #2113Tristan Gingold2022-07-081-41/+47
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* vhdl-evaluation: explicitly compute integer_exp to handle overflow.Tristan Gingold2022-07-071-2/+31
| | | | Tentatively fix crash on mingw32
* vhdl-evaluation: make overflow_literal non locally static.Tristan Gingold2022-07-072-1/+6
| | | | Fix crash in translation (tentatively)
* netlists-disp_verilog: fix output for id_abs. For #2123Tristan Gingold2022-07-061-1/+2
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* synth-vhdl_oper: handle is_x for signed/unsigned. Fix #2129Tristan Gingold2022-07-061-1/+3
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* Fix issue #2126, add handling of to_ux01 to synthesisMichael Nolan2022-07-051-1/+3
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* synth-vhdl_insts: do not crash on unconnected input. Fix #2124Tristan Gingold2022-07-051-0/+4
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* netlists-disp_verilog: handle Id_Abs. Fix #2113Tristan Gingold2022-07-041-1/+1
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* synth-vhdl_insts: also handled unbounded records in hash names.Tristan Gingold2022-07-021-0/+7
| | | | Fix #2119
* vhdl-sem_psl: analyze strong propertiesTristan Gingold2022-07-021-1/+2
| | | | For #2116
* vhdl-sem_names: avoid crash on incorrect selected name.Tristan Gingold2022-07-021-6/+6
| | | | For #2116
* vhdl-sem_decls: avoid crash on self use of a generic package.Tristan Gingold2022-07-021-0/+10
| | | | For #2116
* vhdl: avoid crash on incorrect use of attributes.Tristan Gingold2022-07-025-14/+40
| | | | For #2116
* vhdl: avoid crash on incorrect use of signaturesTristan Gingold2022-07-023-281/+292
| | | | For #2116
* vhdl-evaluation: handle more operations (thought synth).Tristan Gingold2022-07-021-2/+1
| | | | For #2116
* vhdl-sem_names: avoid duplicate error message. For #2100Tristan Gingold2022-06-281-1/+19
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* netlists-disp_verilog: adjust, discard null signals. For #2113Tristan Gingold2022-06-281-1/+6
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* netlists-disp_verilog: fix warningTristan Gingold2022-06-271-1/+2
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* synth/netlists-disp_verilog: skip null input port. Fix #2113Tristan Gingold2022-06-271-15/+20
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* synth: rework #2109 - remove null wiresTristan Gingold2022-06-278-26/+87
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* synth/netlists-disp_verilog: adjust previous patch. For #2109Tristan Gingold2022-06-271-1/+2
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* netlists-disp_verilog: do not display ports of width 0. Fix #2109Tristan Gingold2022-06-271-5/+19
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* Fix nested commentssudden62022-06-261-41/+41
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* vhdl-parse: fix crashes after error. Fix #2110Tristan Gingold2022-06-261-2/+6
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* vhdl-parse_psl: avoid crash on error. For #2110Tristan Gingold2022-06-261-1/+7
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* trans-chap8: adjust conditions to pass parameters. Fix #2104Tristan Gingold2022-06-221-2/+9
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* vhdl-sem.adb: avoid a crash on conformance error. Fix #2103Tristan Gingold2022-06-211-2/+2
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* vhdl-sem_lib: do not disable warnings for files in -c/-rTristan Gingold2022-06-191-1/+5
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* trans-chap7: translate anonymous subtype of overflow literal. Fox #2066Tristan Gingold2022-06-191-2/+6
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* vhdl-sem_expr: check expression index range for aggregate. Fix #2066Tristan Gingold2022-06-191-0/+25
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* synth-vhdl_insts(synth_single_input_assoc): handle type conversion.Tristan Gingold2022-06-162-4/+13
| | | | Fix #2099
* vhdl-sem.adb(are_trees_equal): handle simple aggregate.Tristan Gingold2022-06-161-14/+12
| | | | Fix #2098
* vhdl/translate: handle inertial association in recursive instantiationTristan Gingold2022-06-162-2/+16
| | | | Fix #2065
* vhdl-sem_names: handle element and subtype attributes for type conv.Tristan Gingold2022-06-161-22/+26
| | | | Fix #2097
* vhdl-sem_expr: do not attribute element or subtype attributes as expr.Tristan Gingold2022-06-161-0/+2
| | | | For #2097
* vhdl: handle 'element in 'range. Fix #2071Tristan Gingold2022-06-152-23/+104
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* Add commentsTristan Gingold2022-06-152-1/+2
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* netlists-rename: handle handle signal instances. Fix #2093Tristan Gingold2022-06-153-2/+28
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* src/synth: add netlists.rename to rename identifiers. Fix #2054Tristan Gingold2022-06-144-2/+132
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* netlists-disp_verilog: do not display blackboxes. Fix #2092Tristan Gingold2022-06-131-0/+5
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* netlists-disp_verilog: Use blocking assignments in non-clocked blocksAnton Blanchard2022-06-131-10/+10
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* vhdl: add a parent field to protected_type_declaration. Fix #2091Tristan Gingold2022-06-123-265/+271
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* synth-vhdl_insts: handle actual conversion function. Fix #2090Tristan Gingold2022-06-121-12/+38
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* elab-vhdl_insts: eval inertial expressions to get the type. Fix #2089Tristan Gingold2022-06-122-7/+18
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