iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077	Tristan Gingold	2020-01-11	2	-6/+39
*	synth: fix crash on else-generate. Fix #1076	Tristan Gingold	2020-01-11	1	-3/+10
*	synth: emit error message in case of 'else' for synchronous code. Fix #1074	Tristan Gingold	2020-01-10	1	-10/+10
*	synth: handle ieee.math_real.round Fix #1075	Tristan Gingold	2020-01-10	5	-3/+22
*	synth: consider ports size to create unique instances.	Tristan Gingold	2020-01-10	3	-49/+143
*	synth: emit an error in case of static assertion failure. Fix #1068	Tristan Gingold	2020-01-09	1	-1/+1
*	synth-oper: handle xor for bit_vectors.	Tristan Gingold	2020-01-09	1	-3/+4
*	synth: simplify support of inertial associations.	Tristan Gingold	2020-01-09	6	-5/+24
*	synth: improve support of out/inout variable parameters.	Tristan Gingold	2020-01-08	3	-9/+69
*	vhdl/translate: handle implicit record-record conversions.	Tristan Gingold	2020-01-06	1	-12/+1
*	vhdl/translate: minor refactoring.	Tristan Gingold	2020-01-06	2	-42/+43
*	vhdl: fix multiple reference in trans-chap3.	Tristan Gingold	2020-01-06	1	-2/+6
*	vhdl/translate: handle more partially constrained array subtypes. For #1038	Tristan Gingold	2020-01-06	3	-6/+10
*	vhdl: handle untranslated subtypes for record aggregates. Fix #1051	Tristan Gingold	2020-01-02	1	-3/+12
*	synth: handle scalar inout association for subprograms. Fix #1064	Tristan Gingold	2020-01-02	1	-0/+2
*	vhdl: fix order of std_ulogic literals. For #1063	Tristan Gingold	2020-01-02	1	-3/+3
*	synth-disp_vhdl: handle conversion from signed integers.	Tristan Gingold	2020-01-01	1	-1/+5
*	synth: optimize integer mod for power of 2.	Tristan Gingold	2020-01-01	3	-0/+31
*	vhdl: evaluate std_logic matching equality. Fix #1063	Tristan Gingold	2020-01-01	2	-8/+54
*	vhdl: handle -gGEN=VAL for --synth. Fix #1062	Tristan Gingold	2020-01-01	6	-23/+213
*	synth-inference: merge reset for sub-nets.	Tristan Gingold	2019-12-31	1	-1/+16
*	synth-environment: also optimize mux merge for sub-nets.	Tristan Gingold	2019-12-31	3	-1/+34
*	netlists-disp_vhdl: display iadff.	Tristan Gingold	2019-12-31	2	-7/+19
*	ams-vhdl: add support for 'delayed for quantity.	Tristan Gingold	2019-12-31	9	-144/+197
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	14	-71/+358
*	ams-vhdl: add simultaneous null statement.	Tristan Gingold	2019-12-30	11	-155/+449
*	ams-vhdl: add frequency function, minor fixes.	Tristan Gingold	2019-12-30	6	-6/+26
*	ams-vhdl: handle record nature end name.	Tristan Gingold	2019-12-30	2	-0/+5
*	ams-vhdl: improve error recovery	Tristan Gingold	2019-12-30	6	-61/+92
*	ams-vhdl: analyze, canon and print simultaneous procedural statements.	Tristan Gingold	2019-12-30	6	-90/+175
*	ams-vhdl: fix tree consistency for terminal declaration.	Tristan Gingold	2019-12-30	2	-3/+3
*	ams-vhdl: correctly test and set staticness of dot/integ attributes.	Tristan Gingold	2019-12-30	1	-8/+7
*	ams-vhdl: print subnature declarations.	Tristan Gingold	2019-12-30	1	-1/+16
*	ams-vhdl: check nature for record natures and terminals.	Tristan Gingold	2019-12-30	7	-231/+397
*	vhdl-ams: fix tree consistency for subnature declaration.	Tristan Gingold	2019-12-29	4	-9/+9
*	vhdl-ams: fix overload for simple simultaneous statement.	Tristan Gingold	2019-12-29	3	-4/+26
*	synth: handle wire assigned to a static value. Fix #1058	Tristan Gingold	2019-12-29	3	-9/+104
*	vhdl: improve support of AMS-vhdl (array and record natures, source quantities)	Tristan Gingold	2019-12-28	36	-1059/+5977
*	vhdl: add Has_Delay_Machanism for optional 'inertial' printing.	Tristan Gingold	2019-12-26	6	-93/+165
*	vhdl-prints: subtype indication is optional in object alias.	Tristan Gingold	2019-12-26	1	-3/+2
*	libraries: handle redefinition of a package by an entity.	Tristan Gingold	2019-12-26	1	-75/+80
*	vhdl: handle non-object aliases in selected use clause. Fix #1057	Tristan Gingold	2019-12-24	1	-5/+8
*	synth: handle is_x (as false). Fix #1054	Tristan Gingold	2019-12-24	1	-0/+4
*	vhdl: recognize ieee.std_logic_1164.is_x.	Tristan Gingold	2019-12-24	4	-8/+19
*	ghdlsynth: allow display for libghdl.	Tristan Gingold	2019-12-24	1	-21/+42
*	netlists-disp_vhdl: handle conversion from std_logic to signed/unsigned.	Tristan Gingold	2019-12-24	2	-8/+20
*	netlists-memories: add convert_to_memory.	Tristan Gingold	2019-12-24	1	-298/+504
*	synth: add minor comments.	Tristan Gingold	2019-12-23	2	-1/+3
*	synth: add Get_Input_Instance.	Tristan Gingold	2019-12-14	4	-10/+21
*	netlists-memories: add comments.	Tristan Gingold	2019-12-14	1	-2/+44