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* synth: renaming and minor refactoring.Tristan Gingold2019-09-304-74/+43
* synth: minor refactoring.Tristan Gingold2019-09-301-4/+4
* synth-expr: minor factorisation.Tristan Gingold2019-09-301-25/+19
* vhdl-std_package: reduce cascaded error messages.Tristan Gingold2019-09-301-0/+1
* synth-decls: improve handling of subtype aliases forTristan Gingold2019-09-301-26/+42
* synth: check matching bounds for array equality. Fix #947Tristan Gingold2019-09-303-4/+56
* synth: convert subtype in alias declaration. Fix #946Tristan Gingold2019-09-301-2/+6
* synth: handle alias for is_const. Fix #948Tristan Gingold2019-09-301-2/+3
* synth: handle conversion from slice to unbounded vector.Tristan Gingold2019-09-301-0/+2
* synth: handle while-loop statement.Tristan Gingold2019-09-301-0/+39
* synth: special handling of 'const' functions.Tristan Gingold2019-09-307-16/+134
* synth: slice: avoid crash in case of incorrect slice.Tristan Gingold2019-09-301-4/+4
* synth: refactoring of alias (allow alias of anything).Tristan Gingold2019-09-307-34/+40
* synth: handle slice with index from a record.Tristan Gingold2019-09-301-5/+15
* synth: introduce type_logicTristan Gingold2019-09-296-16/+42
* synth: add support of alias of alias. Fix #945Tristan Gingold2019-09-281-0/+8
* synth: add support for mod operator.Tristan Gingold2019-09-283-24/+30
* netlists-disp_vhdl: improve disp_x_lit.Tristan Gingold2019-09-281-3/+9
* synth-environment: optimize cascaded if.Tristan Gingold2019-09-281-1/+27
* netlists-disp_vhdl: handle id_edge.Tristan Gingold2019-09-281-0/+3
* synth-stmts: simple optimization for loop control logic.Tristan Gingold2019-09-281-10/+19
* synth: disp net number in netlists-dumpTristan Gingold2019-09-281-1/+13
* synth: finalize declarations and free wires.Tristan Gingold2019-09-276-21/+214
* synth: handle range attribute; handle vhdl08 array subtype.Tristan Gingold2019-09-271-19/+25
* synth-environment-debug: improve.Tristan Gingold2019-09-261-1/+2
* synth: handle alias for reshape.Tristan Gingold2019-09-261-0/+2
* synth: do subtype conversion for variable defaultTristan Gingold2019-09-261-0/+2
* synth: do subtype conversion for expression at calls.Tristan Gingold2019-09-262-15/+10
* synth: subtype conversion for selected elements.Tristan Gingold2019-09-261-1/+2
* synth: fix handling of single-bit memories.Tristan Gingold2019-09-262-5/+13
* synth: allow entities with no ports.Tristan Gingold2019-09-251-1/+0
* synth: fix crash on slice of slice.Tristan Gingold2019-09-251-1/+2
* synth-stmts: allow slice as case expression.Tristan Gingold2019-09-251-1/+1
* synth: handle array equality (for constances).Tristan Gingold2019-09-253-1/+22
* synth-disp_vhdl: handle in conversions from bitvector. Fix #940Tristan Gingold2019-09-251-0/+5
* synth-oper: handle not for boolean and bit. Fix #937Tristan Gingold2019-09-251-1/+3
* synth-disp_vhdl: handle disp conversion with bits (and boolean).Tristan Gingold2019-09-251-5/+17
* synth: fixes after previous patch.Tristan Gingold2019-09-254-8/+16
* synth: rework type for expression.Tristan Gingold2019-09-258-226/+250
* synth-inference: optimize for controls.Tristan Gingold2019-09-231-1/+7
* synth: Regenerate ghdlsynth_gates.hTristan Gingold2019-09-231-25/+26
* testsuite/synth: add testcase for previous commit.Tristan Gingold2019-09-221-0/+1
* synth: handle subtype conversions on interfaces.Tristan Gingold2019-09-222-10/+31
* synth: introduce type_unbounded_vector.Tristan Gingold2019-09-224-25/+89
* synth: add more operations.Tristan Gingold2019-09-221-2/+13
* synth: preliminary work for subtype conversions on interfaces.Tristan Gingold2019-09-224-13/+26
* synth: completly disable inference with -di.Tristan Gingold2019-09-221-4/+6
* synth: handle rotate.Tristan Gingold2019-09-224-45/+71
* vhdl: recognize rotate functions.Tristan Gingold2019-09-224-3/+24
* synth: handle exit/next statements.Tristan Gingold2019-09-222-5/+207
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