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* netlists-disp_verilog: fix output of parameter assignments. Fix #1866Tristan Gingold2021-09-151-12/+12
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* netlists-disp_verilog.adb: add 'parameter' before parameters declarationTristan Gingold2021-09-151-1/+1
| | | | For #1866
* synth/netlists-disp_verilog: fix output of parameter values. For #1866Tristan Gingold2021-09-153-12/+37
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* vhdl: move Get_Source_Identifier to vhdl-utilsTristan Gingold2021-09-153-18/+25
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* ortho_code-x86-insns: handle OE_ADD R_I_Off + R_I. Fix #1864Tristan Gingold2021-09-141-0/+7
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* vhdl-sem_expr.adb: adjust aggregate element type extraction. For #737Tristan Gingold2021-09-141-2/+7
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* trans-chap7: improve handling of vector in aggregates. Fix #1493Tristan Gingold2021-09-141-32/+58
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* synth-vhdl_oper: handle nor for booleanTristan Gingold2021-09-141-0/+1
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* trans-chap3: improve commentTristan Gingold2021-09-141-4/+4
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* ortho: for slices, get element size from the result typeTristan Gingold2021-09-1410-17/+76
| | | | | | and not from the object type. Fix #1862
* trans-chap7: improve handling of vector in aggregates. Fix #1453Tristan Gingold2021-09-121-23/+27
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* trans-chap8: fix crash for slice in target aggregate. Fix #786Tristan Gingold2021-09-121-0/+4
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* vhdl-sem_assocs: add a check to avoid a crash on an error. Fix #873Tristan Gingold2021-09-121-0/+4
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* vhdl-canon: recurse for default block configuration of a vunit.Tristan Gingold2021-09-122-19/+25
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* vhdl-configuration: also consider vunits to find top entity.Tristan Gingold2021-09-113-37/+64
| | | | For #1860
* vhdl-configuration: also consider units instantiated in vunit. Fix #1860Tristan Gingold2021-09-111-46/+64
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* synth-vhdl_stmts: fix crash on nested if-generate statement in vunits.Tristan Gingold2021-09-111-2/+5
| | | | Fix #1859
* trans-chap7: improve support of aggregate. Fix #1843Tristan Gingold2021-09-101-10/+29
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* vhdl: allow constants in vunit declarations. Fix #1856Tristan Gingold2021-09-082-0/+3
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* ghdllocal: generalize top level unit extractionTristan Gingold2021-09-075-38/+59
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* vhdl-parse.adb: adjust error message. Fix #1485Tristan Gingold2021-09-071-1/+1
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* options.adb: -Werror now applies on unclassified warnings.Tristan Gingold2021-09-071-0/+1
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* netlists-cleanup: avoid crash when keep attribute value is a stringTristan Gingold2021-09-071-2/+39
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* trans-chap7: Handle unbounded elements in Translate_ConcatenationTristan Gingold2021-09-071-27/+98
| | | | | Fix #1831 Fix #1657
* trans-chap3: add a stride parameter to index_array. For #1831Tristan Gingold2021-09-072-18/+21
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* vhdl/translate: adjust slice names for unbounded arrays. Fir #1836Tristan Gingold2021-09-033-4/+25
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* vhdl-scanner.adb: add commentsTristan Gingold2021-09-031-0/+6
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* vhdl,psl: abort is now identical to async_abort. For #1654Tristan Gingold2021-09-022-6/+4
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* synth-vhdl_stmts.adb: do not expect configuration for vunit.Tristan Gingold2021-09-011-3/+3
| | | | For #1850
* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-313-10/+44
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* trans-chap9.adb: handle async_abort, sync_abort. Fix #1654Tristan Gingold2021-08-305-145/+255
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* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-3019-155/+306
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* vhdl-canon: detect PSL assertion that cannot fail. For #1832Tristan Gingold2021-08-292-3/+17
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* synth-vhdl_stmts: fix a crash on never triggered PSL assertion.Tristan Gingold2021-08-291-0/+6
| | | | For #1832
* synth: improve result of is_positiveTristan Gingold2021-08-294-10/+15
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* netlists-inference: improve location for dff.Tristan Gingold2021-08-291-1/+1
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* synth: factorize code to create base instanceTristan Gingold2021-08-287-57/+104
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* synthesis.adb: abstract instance_passesTristan Gingold2021-08-283-23/+34
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* synth-environment: add subprograms for signals (preliminary work)Tristan Gingold2021-08-282-5/+110
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* synth-memtype: export conversion functionsTristan Gingold2021-08-282-7/+9
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* synth: add build2_concat2 and use it for vhdl concat.Tristan Gingold2021-08-283-4/+18
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* ghdlsynth: add debug option for elaborationTristan Gingold2021-08-282-1/+8
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* synth-vhdl_decls.adb: add commentsTristan Gingold2021-08-281-0/+4
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* vhdl: handle foreign units in libraries and configurationTristan Gingold2021-08-283-24/+45
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* errorout: do not display empty linesTristan Gingold2021-08-283-1/+14
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* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
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* vhdl-parse: support for-generate in vunits. Fix #1850Tristan Gingold2021-08-271-2/+10
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* synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
| | | | For ghdl/ghdl-yosys-plugin#154
* std_names: add name keep.Tristan Gingold2021-08-272-1/+3
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* netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
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