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* vhdl-nodes: do not reset free hooks on initializationTristan Gingold2021-06-263-2/+2
* synth-vhdl_context.adb(Is_Full): consider fractional words.Tristan Gingold2021-06-231-2/+16
* vhdl/Makefile: use python3 by defaultTristan Gingold2021-06-221-1/+1
* synth-vhdl_stmts: add location on AddidxTristan Gingold2021-06-211-0/+2
* synth-environment: early transformation of dyn_insert to dyn_insert_enTristan Gingold2021-06-214-25/+59
* synth-vhdl_stmts: merge static extract before dyn_extract.Tristan Gingold2021-06-211-4/+2
* synth-vhdl_expr: adjust width of memidx for indexed names.Tristan Gingold2021-06-211-1/+1
* vhdl-nodes: Initialize global state to allow restart.Tristan Gingold2021-06-192-0/+4
* vhdl-nodes.ads: use pnodes layout for Number_Base_TypeTristan Gingold2021-06-181-1/+8
* synth: add a gate on an optimization to simplify memory handling.Tristan Gingold2021-06-172-67/+38
* netlists-memories: strengthen dyn_extract mux reduction. Fix #1781Tristan Gingold2021-06-162-1/+52
* synth: minor fixesTristan Gingold2021-06-152-9/+8
* src/ortho/mcode/memsegs_c.c: Don't define HAVE_MREMAP on OpenBSD.Alfred M. Szmidt2021-06-131-1/+1
* vpi: handle get_value for indexed names. Fix #237Tristan Gingold2021-06-105-164/+411
* grt-vpi: add more traces for vpi_register_systfTristan Gingold2021-06-082-5/+19
* grt-vcd: add get_vcd_value_kindTristan Gingold2021-06-083-35/+47
* trans-chap3: add commentsTristan Gingold2021-06-071-2/+10
* grt-vpi: improve support of arraysTristan Gingold2021-06-075-22/+66
* grt: preliminary work to support arrays in vpiTristan Gingold2021-06-065-77/+142
* vpi: handle integer32 signals for vpi_put_value. Fix #1779Tristan Gingold2021-06-052-26/+51
* Fix warnings from gnatgpl 2021Tristan Gingold2021-05-302-2/+2
* vhdl: avoid a crash on forced analysis of a erroneous name expressionTristan Gingold2021-05-282-22/+23
* vhdl-sem_stmts.adb: avoid duplicate error messageTristan Gingold2021-05-281-0/+3
* vhdl-utils: element attribute is a type markTristan Gingold2021-05-251-1/+2
* netlists-memories: avoid a crash on uninitialized ROM.Tristan Gingold2021-05-241-1/+9
* vhdl-scanner: improve column for scanner messagesTristan Gingold2021-05-231-1/+4
* files_map: adjust computation of column for tabsTristan Gingold2021-05-231-2/+1
* vhdl-evaluation: add a commentTristan Gingold2021-05-221-0/+7
* vhdl-evaluation: avoid a crash on null range for enumeration typesTristan Gingold2021-05-211-2/+60
* trans-chap6: add a commentTristan Gingold2021-05-191-0/+1
* ortho_front: use array subtype element if indexing an array subtype.Tristan Gingold2021-05-191-1/+4
* ortho/gcc, ortho/llvm: do not allocate space for unbounded fields. Fix #1764Tristan Gingold2021-05-187-15/+92
* vhdl-sem: handle indexed and slice names. Fix #1768Tristan Gingold2021-05-171-56/+42
* vhdl-utils: an object alias may not have a subtype indication. Fix #1765Tristan Gingold2021-05-161-5/+10
* vhdl: remove unused Get/Set_Alias_DeclarationTristan Gingold2021-05-165-127/+68
* trans-chap4: add commentsTristan Gingold2021-05-161-0/+4
* grt-table.adb: avoid overflow for computing memory size. For #1761Tristan Gingold2021-05-151-5/+8
* trans-chap6: handle alias of unbounded record. For #641Tristan Gingold2021-05-131-1/+2
* ortho: fix CFLAGS/CXXFLAGS distinctionXiretza2021-05-101-1/+1
* ortho: use LDFLAGS and prefer them over defaultsXiretza2021-05-107-9/+8
* grt/Makefile: use CFLAGSXiretza2021-05-101-2/+2
* grt: fix warning about possible constant declarationXiretza2021-05-101-1/+1
* netlists-disp_verilog: fix display of constantsTristan Gingold2021-05-071-10/+20
* std_names: add full and parallel case.Tristan Gingold2021-05-072-3/+7
* synth-environment: add Set/Get_Kind, Wire_UnsetTristan Gingold2021-05-072-1/+26
* netlists-cleanup: do not remove self-assigned output gateTristan Gingold2021-05-071-23/+30
* vhdl-sem_stmts: handle aliases for force/release assignment. Fix #1751Tristan Gingold2021-05-061-5/+8
* netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract.Tristan Gingold2021-05-041-74/+14
* ghdlsynth: never display a foreign module as pure vhdlTristan Gingold2021-04-281-2/+7
* synth: add verilog outputTristan Gingold2021-04-283-0/+1423
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