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* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-051-0/+1
* Add base support for the attribue element in vhdl 08Anselmo952021-04-031-0/+3
* update license headersumarcor2021-01-141-11/+9
* src/vhd: remove use of chapter sign in comment to have on ASCII charactersTristan Gingold2021-01-091-1/+1
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-0/+2
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-4/+4
* vhdl: improve support of subtype attribute.Tristan Gingold2020-07-181-0/+7
* vhdl-utils: minor style changes.Tristan Gingold2020-05-281-4/+2
* vhdl-utils: factorize Get_File_Signature.Tristan Gingold2020-05-151-0/+12
* trans-chap7: Translate_Equality: also convert to base type for records.Tristan Gingold2020-05-131-0/+4
* vhdl-prints: handle evaluated expression for qualified_expression.Tristan Gingold2020-04-181-0/+5
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-0/+8
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-1/+11
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-101-0/+3
* synth: minor rework.Tristan Gingold2019-07-221-0/+4
* vhdl: cleanup in clear_instantiation_configuration.Tristan Gingold2019-07-131-1/+1
* vhdl: move Current_Text from vhdl-utils to vhdl-parse.Tristan Gingold2019-05-251-4/+0
* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-0/+375