iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	1	-3/+4
*	vhdl psl: fully scan PSL keywords in scanner.	Tristan Gingold	2019-08-20	1	-1/+1
*	vhdl-prints: handle architecture in verification unit hierarchical name.	Tristan Gingold	2019-08-20	1	-0/+7
*	vhdl-prints: handle verification units.	Tristan Gingold	2019-08-20	1	-318/+354
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	1	-0/+13
*	vhdl: add PSL keywords to vhdl08 reserved words.	Tristan Gingold	2019-08-14	1	-6/+6
*	vhdl: improve reprint of inertial association.	Tristan Gingold	2019-08-11	1	-1/+5
*	vhdl: handle subtype indication (with range) in discrete_range.	Tristan Gingold	2019-08-10	1	-0/+2
*	vhdl: remove severity from cover, report and severity from assume.	Tristan Gingold	2019-08-08	1	-5/+4
*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-4/+24
*	vhdl-prints: improve output for ports/generics.	Tristan Gingold	2019-07-22	1	-5/+27
*	vhdl: rename Cover_Statement to Cover_Directive.	Tristan Gingold	2019-07-04	1	-6/+6
*	vhdl: parse and analyze restrict directive.	Tristan Gingold	2019-07-04	1	-1/+18
*	vhdl: add anonymous_signal_declaration.	Tristan Gingold	2019-07-03	1	-0/+13
*	vhdl-prints: try to print error content.	Tristan Gingold	2019-06-04	1	-0/+10
*	vhdl-prints: fix extra 'else' in disp_conditional_waveform.	Tristan Gingold	2019-06-03	1	-2/+3
*	vhdl-prints: improve indent.	Tristan Gingold	2019-06-02	1	-0/+4
*	vhdl-prints: improve output for if/then, architecture.	Tristan Gingold	2019-06-01	1	-0/+4
*	vhdl-formatters: add indent.	Tristan Gingold	2019-06-01	1	-1/+5
*	vhdl-prints: handle PSL, add psl tokens for strong and inclusive variants.	Tristan Gingold	2019-05-30	1	-85/+394
*	vhdl: renames disp_vhdl to prints	Tristan Gingold	2019-05-30	1	-0/+4155