| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl-nodes: add Get/Set_Associated_Subprogram. | Tristan Gingold | 2022-11-30 | 1 | -0/+2 |
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| * | vhdl: add Determined_Aggregate_Flag field. For #2166 | Tristan Gingold | 2022-08-10 | 1 | -0/+2 |
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| * | vhdl: add an owner to interface type definition | Tristan Gingold | 2022-08-07 | 1 | -0/+2 |
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| * | vhdl: add support for default in interface subprogram. Fix #2163 | Tristan Gingold | 2022-08-07 | 1 | -0/+4 |
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| * | vhdl-nodes: add Get/Set_Stop_Flag. For #2150 | Tristan Gingold | 2022-07-29 | 1 | -0/+2 |
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| * | vhdl-nodes: add Get/Set_Reference_Terminal_Flag | Tristan Gingold | 2022-07-25 | 1 | -0/+2 |
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| * | vhdl-nodes: renaming. | Tristan Gingold | 2022-07-21 | 1 | -4/+5 |
| | | | | | | | | Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities. | ||||
| * | vhdl-nodes: add Inertial_Flag for association_element_by_expression | Tristan Gingold | 2022-06-12 | 1 | -0/+2 |
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| * | vhdl-canon: add Canon_Add_Suspend_State | Tristan Gingold | 2022-05-26 | 1 | -1/+5 |
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| * | vhdl: parse return identifier (v19) | Tristan Gingold | 2022-03-04 | 1 | -0/+2 |
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| * | vhdl: parse PSL inherit spec. For #1899 | Tristan Gingold | 2021-11-04 | 1 | -2/+2 |
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| * | Add parsing of case? statement and simple test. | Brian Padalino | 2021-09-24 | 1 | -0/+2 |
| | | | | | Also add the Matching flag to the Iir_Kind_Case_Statement. | ||||
| * | vhdl and psl: parse sync_abort and async_abort. For #1654 | Tristan Gingold | 2021-08-30 | 1 | -0/+2 |
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| * | vhdl: remove unused Get/Set_Alias_Declaration | Tristan Gingold | 2021-05-16 | 1 | -2/+0 |
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| * | vhdl: add Iir_Kind_Foreign_Module | Tristan Gingold | 2021-04-05 | 1 | -1/+3 |
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| * | update license headers | umarcor | 2021-01-14 | 1 | -11/+9 |
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| * | vhdl: fix reprint of vhdl08 array element constraints. | Tristan Gingold | 2021-01-05 | 1 | -0/+4 |
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| * | vhdl: handle locally static attributes on entity/architecture/configurations | Tristan Gingold | 2020-12-08 | 1 | -0/+2 |
| | | | | | | | | | | | | | | Attributes of entity/architecture/configurations are expected to be locally static so that they can be referenced from outside (so on the non-instantiated entity). But many designs break this assumption. In relaxed mode, non-locally static attributes are allowed but now cannot be referenced outside the entity. Locally static attributes can be referenced from outside. Fix #1528 | ||||
| * | vhdl: parse subprogram instantiations. For #1470 | Tristan Gingold | 2020-09-24 | 1 | -0/+3 |
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| * | vhdl: parse and analyze force/release signal assignment statements. | Tristan Gingold | 2020-08-01 | 1 | -0/+10 |
| | | | | | For #1416 | ||||
| * | vhdl: replace base_type with parent_type in nodes | Tristan Gingold | 2020-07-22 | 1 | -2/+2 |
| | | | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints. | ||||
| * | vhdl: create default configuration for a vunit. Fix #1372 | Tristan Gingold | 2020-06-15 | 1 | -0/+3 |
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| * | Synthesis of PSL prev function. | Tristan Gingold | 2020-06-02 | 1 | -2/+2 |
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| * | vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662 | Tristan Gingold | 2020-06-02 | 1 | -1/+7 |
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| * | types: introduce Direction_Type, which replaces Iir_Direction. | Tristan Gingold | 2020-04-20 | 1 | -6/+6 |
| | | | | | Global renaming. | ||||
| * | vhdl: add scalar_size. Size of scalar types is computed during analysis. | Tristan Gingold | 2020-04-06 | 1 | -0/+8 |
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| * | synthesis: add option --vendor-library= for synthesis. | Tristan Gingold | 2020-03-10 | 1 | -0/+2 |
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| * | ams-vhdl: handle zoh, ltf and ztf attributes. | Tristan Gingold | 2019-12-31 | 1 | -0/+4 |
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| * | ams-vhdl: check nature for record natures and terminals. | Tristan Gingold | 2019-12-30 | 1 | -0/+2 |
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| * | vhdl: improve support of AMS-vhdl (array and record natures, source quantities) | Tristan Gingold | 2019-12-28 | 1 | -0/+44 |
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| * | vhdl: add Has_Delay_Machanism for optional 'inertial' printing. | Tristan Gingold | 2019-12-26 | 1 | -0/+2 |
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| * | vhdl: add exit/next flags. | Tristan Gingold | 2019-09-18 | 1 | -0/+4 |
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| * | vhdl: renames Conditional_Expression to Conditional_Expression_Chain. | Tristan Gingold | 2019-09-02 | 1 | -2/+2 |
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| * | synth: handle verification units. | Tristan Gingold | 2019-08-20 | 1 | -0/+2 |
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| * | vhdl: declare verification units (WIP). | Tristan Gingold | 2019-08-16 | 1 | -0/+6 |
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| * | vhdl: remove unused Get/Set_Choice_Order. | Tristan Gingold | 2019-08-09 | 1 | -2/+0 |
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| * | vhdl-disp_vhdl: print literals and identifiers from the source. | Tristan Gingold | 2019-05-29 | 1 | -0/+2 |
| | | | | | Add Literal_Length and set it in the parser. | ||||
| * | vhdl: get rid of Get/Set_Physical_Unit. | Tristan Gingold | 2019-05-28 | 1 | -2/+0 |
| | | | | | Use integer_literal for evaluated physical literals. | ||||
| * | psl: add psl-types, psl-nodes_priv. | Tristan Gingold | 2019-05-10 | 1 | -0/+1 |
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| * | vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64. | Tristan Gingold | 2019-05-10 | 1 | -12/+12 |
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| * | vhdl: move nodes_meta package to vhdl child. | Tristan Gingold | 2019-05-06 | 1 | -0/+924 |
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index : iCE40/ghdl | |
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