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* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+10
| | | | For #1416
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-2/+2
| | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-0/+3
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* Synthesis of PSL prev function.Tristan Gingold2020-06-021-2/+2
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* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-1/+7
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* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-6/+6
| | | | Global renaming.
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-0/+8
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* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-0/+2
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* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-0/+4
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* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-0/+2
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* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-0/+44
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* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+2
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* vhdl: add exit/next flags.Tristan Gingold2019-09-181-0/+4
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-2/+2
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* synth: handle verification units.Tristan Gingold2019-08-201-0/+2
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* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-0/+6
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* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-091-2/+0
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* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-0/+2
| | | | Add Literal_Length and set it in the parser.
* vhdl: get rid of Get/Set_Physical_Unit.Tristan Gingold2019-05-281-2/+0
| | | | Use integer_literal for evaluated physical literals.
* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
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* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-12/+12
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* vhdl: move nodes_meta package to vhdl child.Tristan Gingold2019-05-061-0/+924
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