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path: root/src/vhdl/vhdl-nodes_meta.adb
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* vhdl: add Owned_Instance_Package_Body to handle ownershipTristan Gingold2023-03-261-236/+251
* vhdl: make instance_package_body forward_ref, adjustTristan Gingold2023-03-231-1/+1
* vhdl: add Set/Get_Immediate_Body_Flag (for package instantiation)Tristan Gingold2023-03-221-239/+15
* vhdl: add iir_kind_package_instantiation_bodyTristan Gingold2023-03-221-2/+267
* ghdllocal.adb(Build_Dependence): rebuild file dependencies.Tristan Gingold2023-03-131-337/+322
* vhdl: add Get/Set_Elaboration_FlagTristan Gingold2023-01-141-265/+291
* vhdl-sem_inst: handle suspend_stateTristan Gingold2023-01-041-181/+211
* vhdl-parse: handle 'end for' in configuration specification.Tristan Gingold2022-12-211-286/+295
* vhdl: add Get/Set_Associated_package. For #2264Tristan Gingold2022-12-181-185/+200
* vhdl-nodes: add Get/Set_Instantiated_Header.Tristan Gingold2022-12-161-100/+115
* vhdl-nodes: add Get/Set_Associated_Subprogram.Tristan Gingold2022-11-301-183/+205
* vhdl-sem_assocs: handle association with external signal names.Tristan Gingold2022-10-181-62/+64
* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-151-212/+232
* vhdl: add support for file subtype. Fix #2174Tristan Gingold2022-08-111-258/+281
* vhdl: add Determined_Aggregate_Flag field. For #2166Tristan Gingold2022-08-101-134/+149
* vhdl: add an owner to interface type definitionTristan Gingold2022-08-071-185/+200
* vhdl: add support for default in interface subprogram. Fix #2163Tristan Gingold2022-08-071-299/+336
* vhdl-nodes: add Get/Set_Stop_Flag. For #2150Tristan Gingold2022-07-291-116/+138
* vhdl-nodes: add Get/Set_Reference_Terminal_FlagTristan Gingold2022-07-251-204/+219
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-36/+37
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-161-14/+14
* vhdl: avoid crash on incorrect use of signaturesTristan Gingold2022-07-021-281/+285
* vhdl: add a parent field to protected_type_declaration. Fix #2091Tristan Gingold2022-06-121-263/+265
* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-121-302/+317
* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-187/+224
* vhdl-nodes: remove unused fields for procedure declarationsTristan Gingold2022-05-171-219/+210
* vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-171-178/+194
* synth: add support for subtype declaration in vunits. Fix #2033Tristan Gingold2022-04-131-231/+237
* vhdl: parse return identifier (v19)Tristan Gingold2022-03-041-208/+230
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-353/+338
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-041-335/+336
* vhdl: also warns on unused enumeration literalTristan Gingold2021-11-011-209/+211
* Add parsing of case? statement and simple test.Brian Padalino2021-09-241-73/+88
* trans-chap9.adb: handle async_abort, sync_abort. Fix #1654Tristan Gingold2021-08-301-110/+106
* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-107/+133
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-203/+181
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-299/+329
* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-301-101/+98
* vhdl: remove unused Get/Set_Alias_DeclarationTristan Gingold2021-05-161-94/+68
* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-051-317/+366
* vhdl-nodes.ads: reorder fields of block_configuration to match grammarTristan Gingold2021-02-201-1/+1
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-116/+136
* update license headersumarcor2021-01-141-11/+9
* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-255/+285
* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-081-266/+283
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-203/+215
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-201/+259
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-85/+189
* vhdl: adjust hanlding of guard signals for translate.Tristan Gingold2020-07-251-191/+193
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-355/+329
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