iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	synth: handle more signed operations. For #1101	Tristan Gingold	2020-01-19	1	-0/+4
*	vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077	Tristan Gingold	2020-01-11	1	-0/+9
*	synth: handle ieee.math_real.round Fix #1075	Tristan Gingold	2020-01-10	1	-0/+1
*	ams-vhdl: add support for 'delayed for quantity.	Tristan Gingold	2019-12-31	1	-0/+4
*	ams-vhdl: handle zoh, ltf and ztf attributes.	Tristan Gingold	2019-12-31	1	-0/+25
*	ams-vhdl: add simultaneous null statement.	Tristan Gingold	2019-12-30	1	-0/+39
*	ams-vhdl: add frequency function, minor fixes.	Tristan Gingold	2019-12-30	1	-0/+1
*	ams-vhdl: improve error recovery	Tristan Gingold	2019-12-30	1	-0/+1
*	ams-vhdl: analyze, canon and print simultaneous procedural statements.	Tristan Gingold	2019-12-30	1	-2/+7
*	ams-vhdl: fix tree consistency for terminal declaration.	Tristan Gingold	2019-12-30	1	-2/+2
*	ams-vhdl: check nature for record natures and terminals.	Tristan Gingold	2019-12-30	1	-1/+15
*	vhdl-ams: fix tree consistency for subnature declaration.	Tristan Gingold	2019-12-29	1	-4/+4
*	vhdl-ams: fix overload for simple simultaneous statement.	Tristan Gingold	2019-12-29	1	-0/+4
*	vhdl: improve support of AMS-vhdl (array and record natures, source quantities)	Tristan Gingold	2019-12-28	1	-28/+643
*	vhdl: add Has_Delay_Machanism for optional 'inertial' printing.	Tristan Gingold	2019-12-26	1	-0/+11
*	vhdl: recognize ieee.std_logic_1164.is_x.	Tristan Gingold	2019-12-24	1	-0/+3
*	vhdl: recognize sin and cos from math_real.	Tristan Gingold	2019-11-26	1	-0/+2
*	synth: preliminary work to support intrinsic procedures.	Tristan Gingold	2019-11-14	1	-0/+5
*	vhdl: recognize rising_edge/falling_edge.	Tristan Gingold	2019-11-06	1	-0/+3
*	vhdl: allow attributes in vunit declarations.	Tristan Gingold	2019-10-30	1	-0/+2
*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	1	-0/+2
*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	1	-1/+6
*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	1	-0/+13
*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	1	-0/+6
*	vhdl: recognize conv_unsigned from ieee.std_logic_arith.	Tristan Gingold	2019-10-10	1	-1/+7
*	synth: handle package bodies.	Tristan Gingold	2019-10-07	1	-0/+1
*	vhdl: recognize to_bitvector.	Tristan Gingold	2019-10-07	1	-0/+2
*	vhdl: recognize div operators.	Tristan Gingold	2019-09-30	1	-0/+7
*	vhdl: recognize rotate functions.	Tristan Gingold	2019-09-22	1	-0/+5
*	vhdl: add exit/next flags.	Tristan Gingold	2019-09-18	1	-0/+22
*	vhdl-nodes: add a comment.	Tristan Gingold	2019-09-12	1	-1/+1
*	vhdl: recognize numeric_std shift_left.	Tristan Gingold	2019-09-11	1	-0/+5
*	vhdl: recognize numeric_std mul.	Tristan Gingold	2019-09-07	1	-0/+7
*	vhdl: renames Conditional_Expression to Conditional_Expression_Chain.	Tristan Gingold	2019-09-02	1	-3/+4
*	vhdl synth: recognize more operators (add uns log).	Tristan Gingold	2019-09-02	1	-0/+4
*	vhdl: recognize ieee.numeric_std std_match.	Tristan Gingold	2019-08-30	1	-0/+7
*	vhdl: recognize 1164 condition operator, handle in synth.	Tristan Gingold	2019-08-30	1	-0/+2
*	initial support for reduce and/or (#900)	Pepijn de Vos	2019-08-20	1	-0/+4
*	synth: handle verification units.	Tristan Gingold	2019-08-20	1	-1/+13
*	vhdl: parse verification unit (WIP).	Tristan Gingold	2019-08-17	1	-23/+30
*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	1	-6/+58
*	add synthesis support for logic operators on numeric types (#893)	Pepijn de Vos	2019-08-15	1	-0/+21
*	vhdl: improve reprint of inertial association.	Tristan Gingold	2019-08-11	1	-0/+4
*	vhdl: remove unused Get/Set_Choice_Order.	Tristan Gingold	2019-08-09	1	-7/+0
*	vhdl: remove severity from cover, report and severity from assume.	Tristan Gingold	2019-08-08	1	-15/+16
*	vhdl-nodes: gather PSL nodes, regenerate nodes_meta.	Tristan Gingold	2019-08-07	1	-30/+4
*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	1	-5/+12
*	synth: add support for memories.	Tristan Gingold	2019-07-29	1	-0/+2
*	vhdl: linearize analyze and evaluation of concat operators.	Tristan Gingold	2019-07-26	1	-0/+1
*	vhdl+synth: recognize /= to std_logic_unsigned.	Tristan Gingold	2019-07-25	1	-1/+5