| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl: add exit/next flags. | Tristan Gingold | 2019-09-18 | 1 | -0/+32 |
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| * | vhdl: renames Conditional_Expression to Conditional_Expression_Chain. | Tristan Gingold | 2019-09-02 | 1 | -9/+9 |
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| * | synth: handle verification units. | Tristan Gingold | 2019-08-20 | 1 | -1/+17 |
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| * | vhdl: parse verification unit (WIP). | Tristan Gingold | 2019-08-17 | 1 | -2/+3 |
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| * | vhdl: declare verification units (WIP). | Tristan Gingold | 2019-08-16 | 1 | -3/+54 |
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| * | vhdl: remove unused Get/Set_Choice_Order. | Tristan Gingold | 2019-08-09 | 1 | -16/+0 |
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| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code | ||||
| * | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+1 |
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| * | vhdl: parse and analyze restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -0/+1 |
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| * | vhdl: add anonymous_signal_declaration. | Tristan Gingold | 2019-07-03 | 1 | -0/+1 |
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| * | vhdl-disp_vhdl: print literals and identifiers from the source. | Tristan Gingold | 2019-05-29 | 1 | -0/+16 |
| | | | | | Add Literal_Length and set it in the parser. | ||||
| * | vhdl: get rid of Get/Set_Physical_Unit. | Tristan Gingold | 2019-05-28 | 1 | -18/+2 |
| | | | | | Use integer_literal for evaluated physical literals. | ||||
| * | vhdl: add hook on free_node, automatically free | Tristan Gingold | 2019-05-22 | 1 | -10/+33 |
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| * | vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64. | Tristan Gingold | 2019-05-10 | 1 | -26/+26 |
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| * | Make lists a generic package, add vhdl-lists. | Tristan Gingold | 2019-05-09 | 1 | -1/+1 |
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| * | vhdl: move nodes_meta package to vhdl child. | Tristan Gingold | 2019-05-06 | 1 | -1/+1 |
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| * | vhdl: rename iirs to vhdl.nodes | Tristan Gingold | 2019-05-05 | 1 | -0/+6569 |
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index : iCE40/ghdl | |
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