| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl: recognize 1164 condition operator, handle in synth. | Tristan Gingold | 2019-08-30 | 1 | -5/+15 |
| * | initial support for reduce and/or (#900) | Pepijn de Vos | 2019-08-20 | 1 | -5/+18 |
| * | vhdl: extract vhdl.errors from errorout. | Tristan Gingold | 2019-05-08 | 1 | -1/+1 |
| * | vhdl: move ieee packages to vhdl children. | Tristan Gingold | 2019-05-05 | 1 | -0/+319 |
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index : iCE40/ghdl | |
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