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* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-0/+3
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+3
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-0/+4
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-0/+1
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-0/+3
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-0/+2
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-1/+51
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-0/+2
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-0/+4
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-1/+2
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-1/+1
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-0/+1
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-0/+2
* vhdl: add hook on free_node, automatically freeTristan Gingold2019-05-221-4/+0
* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-051-1/+1
* vhdl: move elocations* packages to vhdl children.Tristan Gingold2019-05-051-0/+699