| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+1 | |
| * | vhdl: parse and analyze restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+2 | |
| * | synth: handle vhdl2008 std_logic_1164, handle anonymous_signal. | Tristan Gingold | 2019-07-04 | 1 | -2/+2 | |
| * | vhdl: translate anonymous_signal_declaration. | Tristan Gingold | 2019-07-03 | 1 | -0/+2 | |
| * | synth: handle concurrent assertions. | Tristan Gingold | 2019-07-02 | 1 | -1/+2 | |
| * | vhdl: move annotations from simul to vhdl. | Tristan Gingold | 2019-06-29 | 1 | -0/+1315 | |
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index : iCE40/ghdl | |
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