| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -1/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code | |||||
| * | synth: improve support of vhdl08. Fix #882 | Tristan Gingold | 2019-08-05 | 1 | -1/+9 | |
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| * | synth: unconstrained arrays. | Tristan Gingold | 2019-07-28 | 1 | -0/+3 | |
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| * | synth: preliminary support of dynamic indexing. | Tristan Gingold | 2019-07-28 | 1 | -45/+66 | |
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| * | vhdl annotations: fix annotation of type in interface list. | Tristan Gingold | 2019-07-24 | 1 | -0/+1 | |
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| * | synth: initial support for for-generate statement. | Tristan Gingold | 2019-07-20 | 1 | -5/+8 | |
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| * | synth: do not crash on use of std_logic_1164 2008. | Tristan Gingold | 2019-07-10 | 1 | -10/+4 | |
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| * | vhdl-annotations: partial revert of previous patch for | Tristan Gingold | 2019-07-04 | 1 | -0/+10 | |
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| * | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+1 | |
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| * | vhdl: parse and analyze restrict directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+2 | |
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| * | synth: handle vhdl2008 std_logic_1164, handle anonymous_signal. | Tristan Gingold | 2019-07-04 | 1 | -2/+2 | |
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| * | vhdl: translate anonymous_signal_declaration. | Tristan Gingold | 2019-07-03 | 1 | -0/+2 | |
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| * | synth: handle concurrent assertions. | Tristan Gingold | 2019-07-02 | 1 | -1/+2 | |
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| * | vhdl: move annotations from simul to vhdl. | Tristan Gingold | 2019-06-29 | 1 | -0/+1315 | |
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index : iCE40/ghdl | |
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