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path: root/src/vhdl/translate/trans_analyzes.adb
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* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-1/+3
* trans_analyzes: add support for all processesTristan Gingold2022-05-151-85/+116
* trans_analyzes.adb: reindentTristan Gingold2022-05-121-3/+2
* Fixed some typos (#1868)Patrick Lehmann2021-09-161-1/+1
* update license headersumarcor2021-01-141-11/+9
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+3
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-1/+2
* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-2/+2
* Add simple_IO - to be used instead of Text_IO.Tristan Gingold2019-05-191-3/+3
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
* vhdl: renames iirs_walk to vhdl-nodes_walkTristan Gingold2019-05-081-1/+1
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
* vhdl: move disp_tree and disp_vhdl as vhdl child.Tristan Gingold2019-05-041-2/+2
* Rework list implementation, use iterator.Tristan Gingold2017-11-111-8/+10
* Create default value for ports.Tristan Gingold2017-05-091-2/+1
* vhdl08: allow unaffected in sequential signal assignments.Tristan Gingold2016-11-011-15/+52
* Add translation for selected signal assignment.Tristan Gingold2016-11-011-2/+26
* canon: do not set formal of association by position.Tristan Gingold2016-10-191-8/+2
* Rewrite most of error and warning messages.Tristan Gingold2016-08-021-2/+4
* Add support for conditional assignments.Tristan Gingold2016-01-161-12/+27
* Move translate and simulate.Tristan Gingold2014-11-051-0/+182