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path: root/src/vhdl/translate/trans-chap9.adb
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* vhdl/translate: rework object type elaboration. For #641Tristan Gingold2020-06-241-3/+3
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-1/+1
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-0/+1
* psl: keep denoting names in the PSL ast.Tristan Gingold2020-03-131-1/+2
* ignore restrict in simulation (#897)Pepijn de Vos2019-08-201-15/+14
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-081-4/+14
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-8/+21
* vhdl/translate: reindent.Tristan Gingold2019-07-041-1/+1
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-8/+8
* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-2/+2
* Extract psl-errors from errorout.Tristan Gingold2019-05-101-1/+1
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
* vhdl: move nodes_meta package to vhdl child.Tristan Gingold2019-05-061-2/+2
* vhdl: move ieee packages to vhdl children.Tristan Gingold2019-05-051-2/+2
* vhdl: move std_standard package to vhdl child.Tristan Gingold2019-05-051-1/+1
* vhdl: move canon to a vhdl child package.Tristan Gingold2019-05-051-2/+2
* Remove unused is_ref for choices. Adjust.Tristan Gingold2019-01-021-4/+0
* translate: renaming of Kind_Expr/Get_Ortho_Expr.Tristan Gingold2018-12-111-6/+7
* translate: refactoring.Tristan Gingold2018-11-201-1/+1
* vhdl/translate: improve support of unbounded arrays.Tristan Gingold2018-11-091-2/+2
* trans-chap9: add a guard.Tristan Gingold2018-10-241-0/+9
* trans: avoid translation of coverage report twice.Tristan Gingold2018-10-231-6/+85
* Rework translation of unbounded and complex types.Tristan Gingold2018-10-211-4/+3
* Add Maybe_Ref_Chain (WIP).Tristan Gingold2018-09-201-0/+4
* Fix warning: use clause for package has no effectVicente Bergas2018-05-031-3/+0
* translate: handle anonymous types in formal; handle multiple conversions.Tristan Gingold2018-02-181-8/+22
* Translate; properly separates translation of types from translation of subtypes.Tristan Gingold2018-01-171-19/+23
* sem_inst: fix relocation of instances in instances.Tristan Gingold2017-12-211-0/+1
* Rework list implementation, use iterator.Tristan Gingold2017-11-111-4/+11
* Remove List_Others, cleanup lists.Tristan Gingold2017-11-081-2/+1
* Use Flist for array indexes.Tristan Gingold2017-11-061-0/+31
* Add extended locations (elocations). Still WIPTristan Gingold2017-10-181-1/+0
* Rename In_Conversion/Out_Conversion to Actual_Conversion/Formal_Conversion.Tristan Gingold2017-09-131-1/+1
* Silent spurious warning.Tristan Gingold2017-06-141-0/+5
* Translation: separate subprogram translation spec and body.Tristan Gingold2017-05-181-2/+4
* Create default value for ports.Tristan Gingold2017-05-091-201/+276
* vhdl08: more on unbounded records (WIP)Tristan Gingold2017-02-231-1/+1
* removing PSL coverage hit default reportThomas Hiscock2017-01-051-2/+4
* translate: rename get_array_base to get_composite_baseTristan Gingold2017-01-021-2/+2
* translate: refactoring for ortho_info_type.Tristan Gingold2016-12-301-12/+12
* ownership: check tree after sem and canon.Tristan Gingold2016-11-051-4/+14
* canon: do not set formal of association by position.Tristan Gingold2016-10-191-14/+21
* iirs: rename base_type to number_base_type to avoid confusion.Tristan Gingold2016-10-131-1/+1
* Rework AST to setup ownership and reference policy.Tristan Gingold2016-10-111-1/+2
* iirs: add Forward_Ref linksTristan Gingold2016-09-301-1/+2
* vhdl08: add support of case-generate statementTristan Gingold2016-07-071-91/+326
* Initial support of direct recursive instantiation.Tristan Gingold2016-07-031-5/+17
* PSL: add clocked SERE, make endpoints visible from VHDL.Tristan Gingold2016-03-221-35/+69
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